最佳化離子佈植條件以改善電容耦合式非揮發性記憶體效能

Abstract

非揮發性記憶體元件是半導體產業中廣泛被使用的一種重要的積體電路元件，它存在於各類3C產品與電器用品中，記憶體元件可以被編輯與保存資料，編輯方式分為編程與抹除兩種，影響元件編輯效能最主要的原因是編程效率和抹除的效率，所以我們致力於提升非揮發性記憶體元件的效能。

此實驗是探討電容耦合式非揮發性記憶體元件（CC-NVM）的特性，以CC-NVM為研究標的，藉由製程改良來提升元件的編程與抹除特性。在元件製程中進行以下兩道程序：汲極摻雜與口袋狀佈植時，調整汲極摻雜佈植的參數，讓CC-NVM元件在相同的電壓條件操作下，可以更快完成抹除的程序；另外我們也調整口袋狀佈植的劑量，使元件在電壓條件不變下的情況下，能更快被編程（Programming）。

藉由半導體製程的離子佈植程序的輕汲極參雜與口袋狀佈植的施打劑量與能量等條件來強化記憶體元件的熱載子效應，使元件在進行編程與抹除時，熱載子效應提昇，而得到更快的編程與抹除效率。同時我們對這些離子佈植實驗的CC-NVM元件進行重要的可靠度驗證：數據保存能力測試，觀察元件的數據保存能力不在離子佈植實驗條件改變下是否受影響。

本研究結果顯示，優化離子佈植製程條件不僅顯著提高CC-NVM元件的編輯性能，包括更好的編程和抹除效率，而且還保持了對於該元件的數據保持能力。

Non-volatile memories are important devices in the semiconductor integrated circuit industry. They are embedded in nearly all types of 3C products and electrical appliances. Memory devices are used for data storage and should be readily edited with a high reliability. Editing non-volatile memory devices includes two operation modes: the programming mode and the erasing mode. To optimize the performance of a non-volatile memory device, it is necessary to enhance the programming and erasing efficiencies of the device.

The thesis discusses about the improvement of the editing performance of capacitor coupling non-volatile memory（CC-NVM）devices via optimizing fabrication parameters for efficient reduction in the programming and erasing times. We adjusted the ion implant dosage and energy for the N-type lightly doped drain (NLDD) and the Pocket processes so that the electric field in the CC-NVM device could be properly optimized leading to a better control of the hot carrier effect.

The study shows that optimization of the ion implantation processes not only significantly improves the memory performance of the CC-NVM device, including better programming and erasing efficiencies, but also yields a desirable data retention ability for the device.