分離式閘極非揮發性記憶體技術及新穎多晶矽電子抹除式唯讀記憶體之研究

Abstract

在此論文，首先，我們發展了一種新的方法來作分離式閘極快閃記憶體的寫入及干擾空間的量測。這個方法能幫助我們定量地了解操作空間的變化與電壓的關係，進而，這方法可以用來找到最佳化的寫入條件。由此方法找到的條件可以承受最大的電壓變化。我們成功地運用這方法在新一代的分離式閘極快閃記憶體的發展。 再者，一種新穎的三重自動對準分離式閘極快閃記憶元在此論文被揭露。此記憶元有T型的耦合結構，此新結構能大幅地增加源極和浮動閘極間的耦合電容而不需要記憶元面積的增加，此改善是藉由一個氧化層蝕刻的步驟來調變。此結構能用於寫入電壓的降低及記憶元的縮小。對於寫入電壓的降低，最高電壓可由7.4V降至6.4V。而對於記憶元的縮小，我們成功地降低浮動閘極的長度由0.18µm到0.14µm而沒造成良率的下降或者可靠度的衰退。 最後，一種有著金屬控制閘極的新穎單多晶矽電子抹除式唯讀記憶體EEPROM在此論文中被發表。它的金屬閘極是由嵌刻(damascene)製程作成的鎢(W)線，它的閘極間的介電層是由原子磊晶長成的氧化鋁(Al2O3)。它的寫入/抹除的操作方式和傳統的堆疊閘極(stack-gate)記憶元是相同的，它用通道熱電子注入做寫入及用FN穿隧做抹除。因氧化鋁有著高介電常數的特性，所以我們可以用小於6.5V的電壓來執行寫入及抹除，而此電壓可以用3.3V的元件來操作，而不用使用到傳統的高壓元件。在製程相容方面，此記憶體只需比傳統CMOS製程多出二道光罩既可，此外，這氧化鋁是在後段製程中完成，所以此技術沒有汙染的顧慮以及額外高溫製程所造成的元件影響。因此，此技術非常能適用於嵌入式產品的應用。在此論文中，我們發表了良好的記憶體特性，如快速的寫入及抹除還有良好的重覆寫入/抹除特性及資料持久性。

In this thesis, first, we developed a new methodology for program vs disturb window characterization on split gate flash. This method can help us to understand quantitatively how the window shifts vs bias conditions; furthermore, find the optimal program condition. The condition obtained by this method can withstand the largest program bias variations. This methodology was successfully implemented in the development for new generation of split-gate cell Secondly, a new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling structure is described in this paper. This novel structure can significantly enhance coupling capacitance between the source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6.4 V. For cell size scaling, we successfully reduce the floating length from 0.18µm to 0.14µm without showing the yield loss or reliability degradation. Finally, a novel single poly EEPROM with metal control gate structure is presented in this paper. The control gate is tungsten (W) line made by a damascene process, and inter-gate dielectric is Al2O3 grown by Atomic Layer Deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim (F-N) tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-K material is deposited in the back-end metallization steps, so there is no cross-contamination issue caused by new material nor the device impact induced by the extra thermal cycle from conventional double poly process. Therefore, this new technology is suitable for embedded application. In this paper, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance cycling and data retention.