三維堆疊複晶矽非揮發性記憶體元件技術與分析

Abstract

快閃記憶體是電子產品最重要的記憶單元，為提高記憶容量，記憶元件不斷微縮， 利用電荷捕捉層取代浮動閘極的技術也如火如荼的展開。電荷捕捉式記憶元件的微縮終 究有其極限，因此許多不仰賴電荷儲存的記憶技術應運而生，其中電阻式記憶體(RRAM) 雖然最被看好，然而估計在2020 年之後，才能商品化。如何銜接電荷捕捉式快閃記憶 體和RRAM 之間的空隙，就成為重要課題。近年東芝、三星、旺宏等記憶體大廠都提出 三維結構方案，用較大的元件尺寸增加電荷儲存以及降低干擾。此類元件通道是多晶 矽，晶粒邊界的電荷捕捉陷阱、能量障礙、載子散射，對於記憶體元件有何影響？是亟 待了解的課題。 本計畫擬以三年為期，針對垂直閘極結構的多晶矽記憶體做一通盤了解，包括晶粒 邊界對元件變異的影響、三維記憶體的製作與分析、晶粒邊界缺陷的隨機電報雜訊對記 憶狀態的影響、三維結構的電荷持久與干擾效應等等。第一年度重點為以三維數值模 擬、元件製程開發；第二年度重點為元件記憶特性測試、隨機電報雜訊分析；第三年度 重點為可靠度分析以及記憶性能提升。三維非揮發性記憶體預估在2016 年間開始採用， 本計畫如能順利執行，對於奈米尺度多晶矽元件的物理現象，以及三維記憶體元件的應 用，都可以提供即時幫助。

Flash memory is one of the most important elements of electronic products. In order to increase the memory density, memory cell scales down aggressively. At the same time, the technology of using charge trapping layer to replace the floating gate has been developed extensively. There exists limitation on the shrinkage of the charge-trapping memory cell, thus lots of non-charge-trapping memory cells have been proposed, such as MRAM, FeRAM, PCRAM, and RRAM. Among them, RRAM is the most promising candidate. However, the mass production of RRAM is projected in 2020. How to bridge the gap between RRAM and the current flash memory is a good question. Recently, several 3D NAND flash strategies have been proposed by the major players. 3D NAND flash allows more relaxed design rule to store more electrons and reduce disturbance. However, the channel of the 3D NAND flash becomes poly-Si. Therefore, the impact of traps, potential barrier, carrier scattering due to grain boundary on memory cell becomes urgent. This 3-year project concentrates on the vertical-gate poly-Si 3D NAND flash device. The topics include the effect of grain boundary on device variation, process and characterization of 3D NAND flash devices with various poly-Si grain structure and charge trapping layers, the effect of random-telegraph-noise (RTN) due to grain boundaries on memory states, and the characteristics of charge retention and disturbance of the 3D NAND flash device. In the first year of the project, we will focus on 3D simulation of grain boundary effect and process development. In the second year, devices with various grain structures will be characterized and the RTN will be analyzed. In the third year, we will focus on the charge retention, disturbance, and the improvement of memory performance by the charge-trapping-layer engineering. It is predicted that the 3D NAND flash would be mass-produced in 2016. This project provides deep understand of the fundamentals of the nano-scale poly-Si memory cell and the design, process, and characterization of the 3D NAND flash devices. All of them bring benefit to academic research and industry applications.