極小晶粒與通道厚度於垂直閘極半導體-氧化矽-氮化矽-氧化矽-半導體記憶體元件特性之影響

Abstract

三維堆疊記憶體結構已成為NAND 快閃記憶體發展的主要趨勢，作為通道材料之多晶矽的晶粒大小、數量，以及晶粒邊界的缺陷密度皆會對記憶體特性有所影響。在本論文中，我們製備不同晶粒尺寸與不同通道厚度的垂直閘極SONOS快閃記憶體，並分別探討這二種變因對於記憶體特性的影響。 先前的研究，我們發現有晶粒邊界處，其表面的能帶彎曲較無晶粒邊界的區域小，因此在晶粒邊界處會有較多的壓降落在穿隧氧化層，進而有較快的寫入速度。而當通道中的晶粒邊界數量愈多，則電子被寫入氮化矽的速度愈快，然而，在該研究的最小晶粒大小與通道長度相當，導通電壓及次臨界擺幅的變異性較大。本論文將晶粒尺寸縮小至19奈米，以探討更小晶粒尺寸的影響，晶粒尺寸約19nm。在Fowler-Nordheim 寫入速度與抹除速度比較中，遠小於通道長度的晶粒不僅因為有較多晶粒邊界而有較快的操作速度；另外，由晶粒數目或者晶粒邊界缺陷密度之變異度來主導體的導通電壓變異性和次臨界擺幅變異度也較小。 由於三堆堆疊垂直閘極記憶體，堆疊層數愈多，製程愈困難，且受限於蝕刻技術，最上層元件可能與最下層元件結構相差許多，而使元件的電性變異性提高。因此，我們考量以降低通道厚度來增加在相同蝕刻深度下所能堆疊的層數，以提高單位面積的位元密度。在本論文中，我們發現隨著通道厚度愈薄，多晶矽通道截面的晶粒由不規則形變為柱狀結構，此能減少載子在通道中被晶粒邊界所散射或是捕捉，而有較高導通電流。更重要的是，通道厚度愈薄的記憶體在Fowler-Nordheim寫入速度與抹除速度皆有明顯的增加，藉由TCAD 模擬電場分佈，厚度較薄條件的穿隧氧化層電場愈強，使得操作速度愈快。而抹除狀態的次臨界擺幅變異度上，短通道元件較長通道元件的變異大，我們認為這是由於短通道元件的晶粒數量較少，約4到6顆晶粒，晶粒邊界缺陷密度的變異度會主導次臨界擺幅變異度。 此外，本論文的元件製程中，藉由製程改善，使得通道的尖角區域突出從早期的13 奈米，大幅地減少為6.4 奈米；然而此尖角問題仍然存在，使得元件在經過100次的寫入/抹除 循環後，操作窗口便閉合，且次臨界擺幅也劣化。其原因是進行寫入時，有大量的電子被注入該區域，在多次的循環後，有可能會造成抹除不完全的電子累積，因而使得捕捉電荷的分佈不均勻；此外，由於穿隧氧化層先天的品質不佳，經過多次寫入/抹除循環，穿隧氧化層劣化更快，進而產生大量介面缺陷，導致元件電性劣化。 根據上述結果，縮小晶粒尺寸使之遠小於通道長度，可加快寫入與抹除速度，並改善元件特性均勻度。減少通道厚度雖然也可以加快寫入/抹除速度，但是通道尖角效應增強，對元件耐受度似有不良影響，值得進一步研究。

Three-dimensional (3D) memory structure has been the main trend of NAND flash memory in industry. The grain size, grain number, and grain boundaries of the poly-Si channel may affects the memory characteristics. In this work, we fabricated the vertical gate thin film transistor SONOS (VG TFT SONOS) devices with different grain sizes and different channel thicknesses, and study their on the fresh state, Fowler-Nordeim (FN) programming and erasing speed, and the variations. In the previous research, we found that the grain boundary containing lots of trapping centers may have smaller band bending than the region without grain boundary; thus, the voltage drop on the tunneling oxide at grain boundary will be higher than the other region, and then the programming speed can be enhanced. While the grain number increases in the channel, the speed and the number of electrons being injected into the nitride layer will be increased. However, the smallest grain size in previous work is comparable with the channel length, so the Vth variation and the S.S. variation are large. Therefore, we reduce the grain size to 19 nm and study the effects of such a tiny grain. In the comparison of Fowler-Nordeim programming speed and erasing speed, as the grain size becomes far smaller than channel length, the device not only have faster operate speed because of the large number of grain boundaries but also exhibits smaller Vth variation and S.S variation which are dominated by grain number and the variation of grain boundary trap density. Increasing the total thickness of the stacked layers would increase the process hardness. Furthermore, due to the etching technology limitation, the profiles of topmost device and the bottommost device may differ a lot. Hence, we considered to reduce the channel thickness to increase the stacked layers in the same etching depth. In this work, it is observed that while the channel thickness comes thinner, the grains of the cross section of the poly-Si channel becomes columnar. This reduces the probability that carriers be trapped or be scattered by grain boundary trap, and then the device will have higher on-current. The Fowler-Nordeim programming speed and erasing speed will have obviously improve as the channel thickness gets thinner. According to the TCAD simulation, devices with thinner channel thickness has stronger electric field on the tunnel oxide than devices with thicker channel thickness. The stronger electric field provides faster programming and erasing speed. The S.S. variation of the short channel devices is larger than that of the long channel devices. We suspected that the grain number of short channel devices is few, 4 to 6 grains, so that the grain boundary trap density variation would dominate the S.S. variation. By improving the processes, the protrusion of channel corner is reduced from 13 nm to 6.4 nm. Although this is a notable improvement, the corner effect still degrade the memory endurance seriously. After 100 P/E cycles, the memory window closes and the S.S. becomes progressively worse. This is because of the protruded corner which induces huge numbers of electrons be injected into the corner region and cannot be erased completely. After times of cycle, the un-erased electrons cumulate more and more which may cause non-uniform charge distribution. Also, because of the poor initial quality of tunneling oxide, a lot of interface traps are generated after P/E cycles; thus, the two reasons will deteriorate the electrical characteristics. According to these observations, it is concluded that reducing the grain size to much smaller than the channel length can enhance the program/erasing speed and also improve the uniformity of device characteristics. Decreasing the channel thickness can also enhance the programming/erasing speed. However, it seems that the endurance would be degraded due to the corner effect. Further investigation on the corner effect is suggested.