晶粒結構對於平面與垂直閘極半導體-氧化矽-氮化矽-氧化矽-半導體記憶體寫入速度的影響

Abstract

三維堆疊記憶體結構已成為NAND快閃記憶體發展的主要趨勢。在本論文中，我們製備兩種晶粒尺寸：微小晶粒(TG)和中等大小晶粒(MG)的平面與垂直閘極記憶體，並探討了寫入和抹除速度以及分析了平面閘極元件的上層表面粗糙度和垂直閘極元件的側壁粗糙度。 先前的研究，我們發現在通道界面那有越多的晶粒邊界會提升電場愈強，進而有較快的寫入速度。然而，並沒有考量到晶粒突出的作用。提升寫入速度的主要機制是由於晶粒突出的影響還是晶粒邊界陷阱的影響還是很難被區分。因此，本篇論文的研究動機就是討論對於寫入速度的表現上晶粒尺寸的影響的根本因素。 在平面閘極元件中，TG樣品的寫入以及抹除速度都比MG樣品來的快，除此之外，TG樣品的表面粗糙度幾乎是MG樣品的2.5倍大。因此，當晶粒尺寸變小時，表面會變得更粗糙，進而提升了電場強度導致有較快的寫入和抹除速度。在垂直閘極元件中，在寫入了0.01秒之後，通道長度為0.1微米的TG樣品的寫入速度比MG樣品來的快，而這是因為TG樣品的晶粒數量比MG樣品來的多。然而，通道長度為0.5和1微米的TG樣品的寫入速度似乎是比MG樣品稍快一些，但是並不明顯，而這是因為這兩個樣品之間的晶粒數量差異不大。除此之外，藉由分析TG樣品通道上方的氧化保護層的側壁粗糙度以及MG樣品主動區的邊線粗糙度，我們可以得到一個結論是微影蝕刻的製程步驟是影響大範圍粗糙度的主要原因而晶粒尺寸則會影響小範圍的粗糙度。 從盧立偉學長的碩士論文中，我們可以看出垂直閘極的SOI樣品的寫入速度是比垂直閘極的TG和MG樣品慢上許多，但是他們應該都有類似的大範圍粗糙度。因此，提升垂直閘極SONOS快閃記憶體的寫入速度是和晶粒數量有關聯的，但是大範圍粗糙度明顯地不會影響寫入速度。 在本論文中，所有樣品的小範圍粗糙度從大到小地依序排列為垂直閘極TG樣品、垂直閘極MG樣品、平面閘極TG樣品和平面閘極MG樣品，而這順序和寫入速度一致。當我們在相同晶粒尺寸下比較平面與垂直閘極元件時，它們的晶粒邊界陷阱的影響力是一樣的，但我們卻發現垂直閘極元件的寫入速度會比平面閘極元件來的快，這和小範圍粗糙度的結果一致。因此，晶粒邊界陷阱應該不是提升寫入速度的主要因素，而經過蝕刻導致較為嚴重的通道側向晶粒突出才應該是主要的根本因素。

Three-dimensional (3D) memory structure has been the main trend of NAND flash memory in industry. In this work, we fabricated the planar and VG SONOS memories with two grain sizes: tiny grain (TG) and medium grain (MG), and we studied on the P/E speed and analyzed the top surface roughness of planar devices and the sidewall roughness of VG devices. In the previous research, it is proposed that the more grain boundaries at the channel interface would enhance the local electric field more and then improve the program speed. However, the role of grain protrusion did not be considered. The main mechanism of enhancing program speed is hard to be distinguished between the grain protrusion and the grain boundary traps. As a result, the motivation of this thesis is to discuss the root cause of the effect of grain size on the program speed performance. For the planar devices, the P/E speed of the TG samples is faster than that of the MG samples. Besides, the surface roughness of TG sample is almost 2.5 times larger than that of the MG sample. Thus, when the grain size becomes smaller, the surface roughness becomes worse, and it would enhance the local electric field and lead to the faster P/E speed. For the VG devices, the TG samples with 0.1μm gate length show faster program speed than the MG samples after programming 10-2 second, because the number of the grains of the TG samples is more than that of the MG samples. However, the TG samples with 0.5μm and 1μm gate length seem to show a slightly faster program speed than MG samples, but it is not significant, because the difference in grain number between the TG and MG samples is not large enough. Moreover, by analyzing the channel hard mask sidewall roughness of the TG sample and the line edge roughness of active region of the MG sample, we conclude that the lithography and etching process is the main reason for the long range roughness while the grain size influences the short range roughness. From Mr. Lu’s MS thesis, we can see that the program speed of the VG SOI sample is much slower than that of the VG MG and the VG TG samples, but they should have similar long range roughness. As a result, the improvement of program speed of the VG TFT SONOS memory is related to the number of grains definitely, but the long range roughness does not affect the program speed significantly. In this work, the short range roughness of all samples from large to small is in the sequence of the VG TG samples, the VG MG samples, the planar TG samples, and the planar MG samples. The program speed exhibits the same sequence. With the same grain size, planar versus VG TG samples or planar versus VG MG samples, the effect of the grain boundary traps is the same, but the program speed of the VG samples is faster than that of the planar samples. Therefore, the grain boundary traps should not be the main reason for the enhancement of program speed. The severer grain protrusion resulting from the higher etching rate at grain boundary should be the root cause.