非揮發性快閃記憶體元件電荷分佈與可靠度之探討

Abstract

本論文探討非揮發性快閃記憶體電荷分佈與元件可靠度，主要分為兩個主題，其中主題(一)為P型SONOS快閃記憶體元件氮化矽（Si3N4）儲存電子動態分佈之研究，主題(二)為NAND快閃記憶體隨機電報雜訊對臨界電壓漂移影響之研究。分述如下: 主題(一): P型SONOS快閃記憶體元件寫入藉由通道熱電洞引發熱電子（Channel Hot Hole Induced Hot Electron: CHHIHE）動態寫入機制(Dynamic Programming) 。本研究利用正向讀取（Forward Read: FR）與反向讀取（Reverse Read: RR）量測方法與採用三維元件模擬，來監測記憶體在動態寫入時氮化矽儲存電子均勻程度，並研究動態寫入機制儲存於氮化矽的電子分佈情形。結果發現，藉由通道熱電洞引發熱電子動態寫入機制，通道熱電子注入點從元件汲極延伸至源極，造成儲存於氮化矽的電子分佈在短暫的寫入時間內，展延至整個氮化矽層，顯示通道熱電子在P型SONOS記憶體元件可以均勻注入並儲存。此特性有別於N型SONOS記憶體元件，其注入電子被局部束縛於氮化矽層。 主題(二): 近年來NAND快閃記憶體元件尺寸不斷微縮，已經來到次奈米級世代，在記憶體讀取操作下，隨機電報雜訊(Random Telegraph Noise: RTN)影響元件之臨界電壓漂移(Threshold Voltage Fluctuation)特性最為嚴重。RTN效應主要是SiO2/Si介面缺陷(Interface Trap)導制通道載子被補捉進而影響臨界電壓漂移。元件尺寸微縮效應下，為了防止元件短通道效應(Short Channel Effect)以及寫入擾動(Program Disturbance)，迫使降低元件源極汲極區(Source/Drain)的摻雜濃度。本論文首次討論不僅考慮元件通道區，並同時考慮源極汲極區，隨機電報雜訊對元件特性擾動之影響。利用三維蒙地卡羅(Monte Carlo)分析法，同時考慮隨機摻雜擾動(Random Dopant Fluctuation: RDF)與隨機電報雜訊(RTN)效應在元件通道與源極汲極區對元件臨界電壓漂移特性之影響。本研究結果發現，缺陷會隨不同的位置影響元件臨界電壓漂移的大小。尤其在源極汲極區影響臨界電壓漂移及為嚴重。本研究同時也考慮，在(Shallow Trend Isolation: STI)製程下當記憶體元件形狀有所改變時對隨機電報雜訊之影響。

This thesis investigates the trapped charge distribution and reliability issues in non-volatile flash memory devices. It consists of two research topics: one is the study of trapped charge distribution in p-channel SONOS memory device using dynamic programming scheme, and second is the impact of source/drain junction and cell shape on random telegraph noise in NAND flash memory. The abstract of each investigation is organized as follows. PART A: In this study, we precisely investigate the charge distribution in Si3N4 layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon–oxide–nitride–oxide–silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in Si3N4 layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in Si3N4 layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking. PART B: A comprehensive numerical study of threshold voltage fluctuation (ΔVT) in scaled NAND flash memory caused by random telegraph noise (RTN) and discrete dopant fluctuation (RDF) in both the channel and the cell-to-cell space (source/drain (S/D)) region was carried out. Following a three-dimensional (3D) Monte Carlo (MC) procedure, the statistical distribution of ΔVT is estimated, considering the effects of both the random placement of discrete doping atoms and a discrete single trap at the tunnel oxide/substrate interface. The result demonstrates the significant influence of the doping in the S/D regions. For the cells with and without an S/D junction, the electron concentration in the S/D region is determined by the pass voltage of the unselected cell (Vpass) and the neighboring cell VT (VT(n)), owing to the fringing fields of neighboring floating gates (FGs). As a result, ΔVT increases in the S/D region as Vpass -VT(n) decreases. The fluctuation amplitude strongly depends on the single-trap RTN position along the cell length (L) and width (W) directions. For the cell shape with rounding of the active area (AA) at the shallow trench isolation (STI) edge, the results indicate that the high VT area moves from the AA edge towards the center area along the W-direction.