標題: Novel single-poly EEPROM with damascene control-gate structure
作者: Sung, HC
Lei, TF
Hsu, TH
Wang, SW
Kao, YC
Lin, YT
Wang, CS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: atomic layer deposition (ALD);damascene;EEPROM;single poly
公開日期: 1-十月-2005
摘要: A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al2O3 grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-kappa material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.
URI: http://dx.doi.org/10.1109/LED.2005.856014
http://hdl.handle.net/11536/13218
ISSN: 0741-3106
DOI: 10.1109/LED.2005.856014
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 26
Issue: 10
起始頁: 770
結束頁: 772
顯示於類別:期刊論文


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