二矽化鈷製程之研究

Abstract

金屬矽化物早已成為半導體元件製程中導線與接觸之材料。在180 nm以後鈷矽化物被廣泛使用。因鈷矽化物窄線寬效應、低電阻率與良好的熱穩定度有免疫力，所以鈷矽化物是近來最被廣泛使用在自我為準矽化技術的材料。然而，隨著元件尺寸不斷地縮小至深次微米，物理結構產生的壓力已經明顯地影響鈷矽化物的形成。在形成鈷矽化物期間，由於固態反應與體積變化作用，使鈷原子成為主要的擴散物質。 根據本實驗的研究結果，因物理結構的影響產生張應力使鈷原子往側向擴散而形成Gate spacer下方凹陷問題及明顯的短通道效應(Short Channel Effect)形成嚴重的漏電(Leakage)問題。本論文針對目前產品所使用的物理結構形成鈷矽化物而遭遇到的問題列為主要的研究主題。 因此本實驗利用形成鈷矽化物的製程中，透過改變不同的製程參數條件，如：RAT1 Anneal的時間(30s、60s、90s)及RAT2 Anneal的溫度(650℃+725℃、725℃、740℃)與時間(60s+30s、60s、30s)還有Co Sputtering的厚度(115A、90A、95A、135A)與溫度(100℃、300℃)之參數，製備出不同參數條件的鈷矽化物，再將製備完成的wafer samples，利用電性測量自動機台與TEM及EDX切片分析，發現改變Co Sputtering溫度，能有效地改善Gate Spacer film 與 silicon 所產生的張應力，使目前遭遇到的問題得以解決。

Metal silicides have been developed as interconnect and contact materials for semiconductor device fabrication. CoSi2 is the most widely used material for silicide technology after 180nm, since it has immunity to narrow line width effect, lower resistivity and good thermal stability. However, with the continued scaling down of device features, the stress induced by physical structures has noticeable effect on the formation of CoSi2 in deep sub-micron ULSI technology. During the growth of CoSi2, it has been reported that the main diffusing specie is Co atom for the solid phase reaction and volumetric change. We found the diffusion of Co atoms is also affected by the stress. The results show as follows. The tensile stress effect of gate spacer film and silicon interface for the formation of CoSi2 physical structures, induced Co atoms diffusion to under gate spacer. The Co atoms diffusion induced under gate spacer void、the drain-to-source junction leakage current and short-channel effects problem. In this thesis, the formation of CoSi2 affected by product physical structures induced problem has been studied in detail. The used different process parameters condition of cobalt silicide formation process of this studied. Example RAT1 Anneal process time(30s、60s、90s)、RAT2 anneal process temperature (650℃+725℃、725℃、740℃)/ RAT2 anneal process time (60s+30s、60s、30s) and Co Sputtering deposition thickness(115A、90A、95A、135A)/ Co Sputtering process temperature(100℃、300℃) then the wafer samples to do electrical characteristic measurement、cross-sectional TEM and EDX analysis . The results show as follows. The tensile stress effect induced Co diffusion to under gate spacer. The Co Sputtering deposition process temperature can effectively improvement, the current encountered problems also can be solved of product.