嵌入式圖形處理器之設計與實作

Abstract

The present work introduces an embedded GPU simulator based on ATTILA, an open source GPU simulator project. Indeed, the rapid and exponential growth of the embedded market requires us to adapt us to its specific needs: restricted power consumption, bandwidth, memory and silicon area. However, there is no existing open source simulator for embedded GPU whereas embedded and desktop architectures are differing more and more. Therefore, we propose to integrate a tile accelerator inside ATTILA in order to adjust its architecture to the current embedded GPU. Indeed, tiling architectures have been leading embedded GPU market in recent years. We first analyze the different specificities of those architectures before proposing an implementation of some of them inside our simulator. The implementation is separated between the timing simulator, which models the hardware structure, and the functional emulator, which reproduce the behavior of the program. Afterwards we set our simulator as Power GPU, the current reference in term of tiling architectures, and perform tests against real PowerVR GPU. We finally use our simulator to show the impact of the display list's size on the number of cycles required to process a frame. Hence, the simulator can be used in future research about embedded GPU architecture by providing a highly configurable graphic pipeline and several hardware statistics.

本文GPU模擬器是基於ATTILA嵌入式GPU開源計畫進行開發。為了因應迅速成長的嵌入式市場，必須將重點擺放在低功耗、頻寬、記憶體以及矽片面積。但截至目前為止並沒有針對嵌入式GPU模擬器的開源計畫，因此我們提出將tile accelerator整合進ATTILA，以符合目前嵌入式GPU架構的模擬器。而tiling架構已經在嵌入式GPU市場行之有年。 在實作模擬器前，我們先分析不同架構下的不同特性。實作分為timing simulator與functional simulator，timing simulator用來建構硬體模型，functional simulator用來重現程式的行為。 我們模擬PowerVR GPU，並實際在PowerVR GPU上測試。我們利用模擬器來顯現display list size對處理一個frame花的cycle數的影響。 因此，我們的模擬器可供未來研究嵌入式GPU使用，同時提供高度可調graphic pipeline以及詳細的hardware counters。