應用於可攜型嵌入式晶片系統之高效能電源管理策略

Abstract

隨著可攜型嵌入式系統的蓬勃發展，其相關電子產品廣泛應用於日常生活之通訊、教育、娛樂、生醫量測…等領域。除功能上不斷創新與微型化的設計導向外，如何增加可攜型電子裝置之使用待機時間亦趨成為一重要設計課題。因此嵌入式晶片系統之電源模組與電源管理策略遂成為系統設計極重要的一個環節，其不僅需具備高質量轉換效率與低使用體積之特性，更必需考量整體嵌入式系統之動態工作負載，適時的優化電源模組輸出功率，以期延展可攜式電子產品的運作時間。而可攜型嵌入式系統的核心元件—微處理器，即為此動態工作負載之控制核心。 在傳統的動態電壓調節電源管理策略中，作業系統依據目前系統工作負載之寬鬆時間動態調節電源模組供給微處理器之操作電壓，以達成節能省電目標。故若在系統不存在寬鬆時間狀況下，此電源管理策略即無法運行。而本論文提出基於指令週期之動態電壓調節技術，配合高速非同步電壓調節之降壓直流穩壓器嵌入設計於微處理器核心，即可突破此項限制。實驗以此電源管理策略整合於數位信號處理晶片系統中，結果顯示平均可節省53%之微處理器功率消耗。 另一方面，為了符合多媒體嵌入式系統在擴音應用之效率需求，本論文尚提出應用於可攜型揚聲系統的D類功率放大器—內插式脈波寬度調變技術。其特有的脈寬調變技術，可使調變指數趨近於1，在實驗結果顯示不採用量化誤差塑形迴路濾波器架構下仍保有108dB之訊噪比，對比基於調變指數僅0.5之傳統三角積分調變器架構所設計的數位D類放大器，其最大輸出功率可提升至2.2倍。 本論文所提出的各種電路與電源管理策略，均以全數位標準互補式金屬氧化物半導體製程實現，實驗結果顯示非常適用於前瞻之次微米嵌入式系統晶片之電源與功率模組整合需求。

Due to continuous flourish of portable embedded systems, related electronics are widely developing in our daily life, such as communication, education, entertainment, biomedical measurement, and etc. In addition to on-going innovative features and miniaturization, design orientation is how to extend the standby interval in these embedded systems for power saving, which has become a critical design issue. Therefore, power management unit with power management strategy in portable embedded system-on-a-chip (SoC) applications becomes a very essential design area. Small-volume power management unit with power management strategy not only needs to keep the characteristics of high-quality conversion efficiency, but also considers real-time overall embedded system dynamic workload to adaptively optimize output power. It can lead to significant improvement in service time of portable electronics. Here, the exact control source of the dynamic workload is core component of portable embedded systems, which is digital signal processor (DSP) or microprocessor. Conventional task-based dynamic voltage scaling (DVS) power management strategy allows all tasks in a scheduler to complete just-in-time operations. Thus, the operating system (OS) depends on run-time workload and dynamically adjusts the power module output voltage, thereby leading to substantial power saving in processor. Unfortunately, conventional task-based DVS fails to operate if the microprocessor has no slack time. To overcome the limitation, this thesis proposed an instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy with swift response and low quiescent current lattice asynchronous self-timed control digital low-dropout (LASC DLDO) regulator for low-power processor designs. Experiment results show that the iDVS-based DSP chip achieves 53% power saving. On the other hand, Class-D amplifiers are prevalent in portable audio embedded systems due to high power efficiency. Thus, battery lifetime can be extended and thermal dissipation can be reduced. This thesis also presented a differential interpolation pulse-width modulation (iPWM) based Class-D acoustic amplifier for multimedia embedded SoC systems. Without noise shaping feedback loop, the iPWM based Class-D modulator can have 108 dB signal-to-noise ratios (SNR). It also implies that modulator is always stable for full-swing input audio signal corresponding to modulation index approximately equal to one. Experimental results demonstrate that iPWM maximizes Class-D switching amplifier output power with 2.2 times that of traditional digital sigma-delta modulator based Class-D amplifier with modulation index 0.5. In system-level and circuit-level perspectives, the proposed power module and power management strategy are all implemented in fully digital standard complementary metal oxide semiconductor (CMOS) process. Experimental results show that it is appropriate for highly integrated SoC as well as for advance sub-micrometer chip power management module embedded system integration.