隨機二位元與非二位元低密度同位元檢查碼解碼器之研究

Abstract

為了確保傳輸與儲存的可靠度，錯誤更正碼在通訊和儲存系統中變得不可或缺。在錯誤更正碼中，低密度同位元檢查碼因其優越的錯誤更正能力及較高的解碼吞吐量而受到學術界及產業界的矚目。近年來，許多的通訊標準爭相採用了多碼率的低密度同位元檢查碼以應付不同的傳輸環境。然而，支援多碼率的解碼器在實作上會遇到繞線的挑戰，使得晶片面積與操作頻率的效能變差。隨機解碼藉由位元序列的特性及簡單的運算單元而能巧妙地提供低密度同位元檢查碼解碼器具有高繞線效益和緊密的晶片面積。另一方面，相較常見的二位元低密度同位元檢查碼，非二位元低密度同位元檢查碼具有較佳的錯誤更正能力，但是伴隨解碼複雜度過高及吞吐量太低的缺陷；如何達到每秒億位元的解碼吞吐量同時又能降低儲存需求仍是隨機解碼的設計課題。在本論文裡，吾人提出了數個具有高面積效益的隨機解碼技巧，並透過電路實現展示隨機解碼器的高度競爭力。 針對二位元低密度同位元檢查碼，我們呈現全世界第一顆透過矽晶片驗證，支援IEEE 802.15.3c應用之多碼率隨機解碼器晶片。此解碼器使用了可變節點的硬體架構及運算單元的簡化來提昇操作頻率、面積效益與能量效益，因此解碼器可操作在768MHz的時脈，同時達到高吞吐量的情境。另外，為了支援不同碼率與權重的需求，根據同位元檢查矩陣和隨機運算的特性而提出繞線網路重排的技巧來提升晶片利用率。考量到晶片測試的不穩定性，本晶片亦將編碼器、高斯通道產生器與解碼器整合為一完整編解碼器系統；同時也設計了一個具有獨立電源區域的延遲鎖相迴路來提供晶片內部高速且穩定的時脈源。根據前述特色，此晶片透過聯電90奈米下線並經由CIC數位量測機台進行量測，結果顯示此解碼器的晶片面積為2.67mm2，可達到90%的晶片利用率；在供應電壓為1.2V下，可以達7.92Gb/s之晶片吞吐量且僅有437.2mW的功率消耗，相對應的面積效益及能量效益為2.97Gb/s/mm2與55.2pJ/bit。相較於現有應用於IEEE 802.15.3c的解碼器中，本設計可達到最高的硬體效益及能量效益。 針對非二位元低密度同位元檢查碼，我們提出了一顆(168, 84)、(2, 4) 規律、在有限域GF(16)上的隨機解碼器晶片，藉由優化的解碼演算法及節點單元、對數域轉換、訊息截斷、解碼排程重整等技術來降低運算複雜度、減少位元長度與記憶體的用量，並提升解碼器吞吐量。所提架構亦透過聯電90奈米下線並經由CIC數位量測機台進行量測，晶片面積為3.75mm2且晶片利用率達96.6%；在供應電壓為1.2V及室溫操作下，晶片吞吐量可達到1.31Gb/s且功率消耗為587.7mW。針對能量感知之應用，晶片可操作在0.8V的供應電壓、194MHz的時脈下，達到最佳的能量效益0.29nJ/b。相較於現有非二位元解碼器中，本晶片在功率消耗、面積效益、能量效益分別可提昇6倍、2倍、7.5倍的效能。

To ensure the reliability of transmission and storage, error-control codes are requisite in communication and storage systems. Among error-control codes, low-density parity-check (LDPC) codes, due to its excellent error-correcting performance and throughput, are very attractive to academia and industry. Recently, the multi-rate LDPC codes are widely adopted in a variety of specifications to support different transmission schemes. However, the design challenge of a multi-rate LDPC decoder is wire routing, which affects the size of area and the operating frequency. Stochastic decoding cleverly provides a routing efficient and compact solution for LDPC decoders by means of bit-serial property and simpler computations. On the other hand, nonbinary LDPC (NB-LDPC) codes can provide even better coding gain than binary LDPC codes at the cost of higher decoding complexity and lower throughput. How to achieve a throughput of Gbps as well as reduce the storage requirement remains key design challenge for stochastic decoding. In this dissertation, we propose an area/energy-efficient stochastic decoding for binary and nonbinary LDPC codes and demonstrate our proposals are competitive to conventional LDPC decoding algorithms. For binary LDPC codes, the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications is presented. The critical path is improved by a reconfigurable stochastic check node unit (CNU) and variable node unit (VNU); therefore, a high throughput scheme can be realized with 768 MHz clock frequency. To achieve higher hardware and energy efficiency, the reduced complexity architecture of tracking forecast memory is experimentally investigated to implement the variable node units for IEEE 802.15.3c applications. Based on the properties of parity check matrices and stochastic arithmetic, the optimized routing networks with re-permutation techniques are adopted to enhance chip utilization. Considering the measurement uncertainties, a delay-lock loop with isolated power domain and a test environment consisting of an encoder, an AWGN generator and bypass circuits are also designed for inner clock and information generation. With these features, our proposed fully parallel LDPC decoder chip fabricated in 90-nm CMOS process with 760.3K gate count can achieve 7.92Gb/s data rate and power consumption of 437.2mW under 1.2V supply voltage. Compared to the state-of-the-art IEEE 802.15.3c LDPC decoder chips, our proposed chip achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively. For nonbinary LDPC codes, a partial parallel decoder of a (168, 84) regular-(2, 4) NB-LDPC code over GF(16) is implemented. The simpler routing networks profited from stochastic computation with optimized computation units deliver 96.6% logic utilization which is the highest value of silicon-proven LDPC or NB-LDPC decoders. The logarithm domain transformation as well as a message truncation technique is proposed to further reduce the bit-width and storage requirement of messages. A test chip was fabricated in UMC 90-nm 1P9M CMOS process with core area of 3.75mm2. At the standard performance condition with room temperature and 1V supply, the chip can be operated at 264MHz, achieving a throughput of 943.7Mb/s with 188 computation cycles and consuming a power of 347.1mW. For better area efficiency, we increase the supply voltage to 1.2V, where a clock rate of 368MHz is achieved for a higher throughput of 1.31Gb/s and an area efficiency of 350.67Mb/s/mm2. For energy-aware applications, we scale down the supply voltage to 0.8V for a lower operating frequency of 194MHz, leading to the best energy efficiency of 0.29nJ/b (associated with a power of 203.5mW). Compared to the latest NB-LDPC designs, the power consumption, area efficiency and energy efficiency of this chip are 6x, 2x, and 7.5x better, respectively.