標題: | An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes |
作者: | Lee, Xin-Ru Yang, Chih-Wen Chen, Chih-Lung Chang, Hsie-Chia Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Nonbinary low-density parity-check (LDPC) codes;relaxed half-stochastic (RHS) algorithm;stochastic decoding |
公開日期: | 1-三月-2015 |
摘要: | This brief presents an area-efficient relaxed halfstochastic nonbinary low-density parity-check (NB-LDPC) decoder. A novel decoding algorithm, namely, cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-errorrate performance as well. Furthermore, the hardware complexity of variable node units (VNUs) is reduced through a truncated architecture, which only keeps the most reliable n probability density functions. To deal with the sum-product-algorithm-to-stochastic conversion of VNU, a dynamic random number generation method, which is used for sampling a stochastic symbol, is also proposed. With these features, a (168, 84) regular-(2,4) NB-LDPC code over GF(16) decoder is implemented in a 90-nm process. According to the results of postlayout simulation, this decoder can deliver a throughput of 1.13 Gb/s with a hardware efficiency of 0.90 Mb/s/K-gate at 286 MHz. Compared to related rate-1/2 NB-LDPC decoders, the proposed decoder achieves the highest hardware efficiency with similar error-correcting capability. |
URI: | http://dx.doi.org/10.1109/TCSII.2014.2368616 http://hdl.handle.net/11536/124555 |
ISSN: | 1549-7747 |
DOI: | 10.1109/TCSII.2014.2368616 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
Volume: | 62 |
起始頁: | 301 |
結束頁: | 305 |
顯示於類別: | 期刊論文 |