標題: An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm
作者: Lin, Chia-Lung
Tu, Shu-Wen
Chen, Chih-Lung
Chang, Hsie-Chia
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Decoding scheduling;extended min-sum (EMS) algorithm;nonbinary low-density-parity-check (NB-LDPC) codes;very large scale integration (VLSI)
公開日期: 九月-2016
摘要: Nonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, provide stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms have been proposed in the literature, and the extended min-sum (EMS) algorithm is the one with minimal performance loss. In this brief, we present an efficient decoder architecture for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but also overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed as well. With these schemes, the postlayout results of a decoder for a (112, 56) NB-LDPC over GF(64) are presented. The core area occupies 2.24mm(2) and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware efficiency and energy efficiency.
URI: http://dx.doi.org/10.1109/TCSII.2016.2534820
http://hdl.handle.net/11536/134066
ISSN: 1549-7747
DOI: 10.1109/TCSII.2016.2534820
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 63
Issue: 9
起始頁: 863
結束頁: 867
顯示於類別:期刊論文