非二進位之低密度同位檢查碼的解碼器設計與實作

Abstract

由低密度同位檢查碼衍伸而來的非二進位低密度同位檢查碼，不僅具有極佳的錯誤更正能力，並且在通訊品質較差的傳輸環境下更能克服通道的雜訊。非二進位低密度同位檢查碼具有極佳的解碼能力，但是複雜的運算以及大量的記憶體需求，是其硬體實現上急需克服的問題與挑戰。在本篇論文中，應用可以加速收斂速度的分層解碼架構，我們提出了具有高硬體效能的非二進位低密度同位檢查碼的解碼器設計。根據擴展最小和算法(EMS)的解碼演算法，我們在檢查點(CNU)的運算上使用雙倍吞吐量去提升整體解碼器的運算速度，並善加利用同位檢查矩陣(H)本身的結構特性，使所需的訊息儲存量縮減為原本的一半。最後，利用UMC 90奈米CMOS製程，我們實作了一個(112,56)，應用在GF(64)下的非二進位低密度同位檢查碼之解碼器來展示我們的構想，與目前其他研究的成果相比，我們所提出的解碼器架構，在硬體效能上擁有至少4倍以上的優勢。

Non-binary LDPC codes which extended from binary LDPC codes have ex- cellent decoding performance, and it is robust to various channel impairments. With the remarkable decoding ability, the high computational complexity and huge memory usage are the main challenges for non-binary LDPC codes to be imple- mented in practical. This thesis presents a high hardware efficient architecture for implementing non-binary LDPC decoder using improved Extended Min-Sum de- coding algorithm with layered scheduling. Based on the enhancement in the check node processing and efficient memory storing, the proposed decoder can double the throughput and have half reduction in storing the edge messages. Using 90- nm CMOS process technology, a (2,4)-regular non-binary QC-LDPC decoder over GF(26) is implemented. In the post-layout simulation results, the decoder through- put can reach over 100 Mbps at 10 iterations. Compared with state-of-the-art de- signs, this implementation has at least 4.3 times improvement in hardware effi- ciency (throughput-to-gate-count-ratio), and the decoding performance still keep competitive.