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dc.contributor.authorLin, Chia-Lungen_US
dc.contributor.authorTu, Shu-Wenen_US
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2017-04-21T06:56:11Z-
dc.date.available2017-04-21T06:56:11Z-
dc.date.issued2016-09en_US
dc.identifier.issn1549-7747en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSII.2016.2534820en_US
dc.identifier.urihttp://hdl.handle.net/11536/134066-
dc.description.abstractNonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, provide stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms have been proposed in the literature, and the extended min-sum (EMS) algorithm is the one with minimal performance loss. In this brief, we present an efficient decoder architecture for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but also overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed as well. With these schemes, the postlayout results of a decoder for a (112, 56) NB-LDPC over GF(64) are presented. The core area occupies 2.24mm(2) and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware efficiency and energy efficiency.en_US
dc.language.isoen_USen_US
dc.subjectDecoding schedulingen_US
dc.subjectextended min-sum (EMS) algorithmen_US
dc.subjectnonbinary low-density-parity-check (NB-LDPC) codesen_US
dc.subjectvery large scale integration (VLSI)en_US
dc.titleAn Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithmen_US
dc.identifier.doi10.1109/TCSII.2016.2534820en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFSen_US
dc.citation.volume63en_US
dc.citation.issue9en_US
dc.citation.spage863en_US
dc.citation.epage867en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000382684700011en_US
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