應用於非二位元低密度同位元檢查碼之高面積效率隨機解碼器

Abstract

非二進位低密度同位元檢查碼是由低密度同位元檢查碼延伸而來的，不僅具有極佳的錯誤更正能力且擁有抵抗連續錯誤能力，最近，隨機演算法運用在非二進位低密度同位元檢查碼的解碼有很大的發展性。雖然可以藉由隨機運算中用一連串的符號來表示機率值，來降低複雜度，但複雜的運算和大量的記憶體需求，仍不利於硬體實作。在此論文中，提出了三種不同的隨機解碼器，分別使用三種不同的演算法，且都用90奈米製程來實現。藉由論文中所提到的方法，可以有效的降低運算複雜度和記憶體使用量，來達到高的面積效率。論文的最後，實現了一顆針對(168,84) 應用於GF(32) (2,4)規律的非二進位低密度同位檢查碼解碼器的晶片。其包含測試考量的面積為3.75mm2且晶片密度可以達到96.6% ，從量測結果可以得知，此1014k邏輯閘的解碼器在時脈為368MHz下，吞吐量是1.32Gb/s、功耗為588mW。與目前其他研究的成果相比，這顆晶片不僅在硬體效率有2倍的優勢，甚至在能量效率有7倍的優勢。且就我們所知，這是第一顆利用隨機演算法在非二進位低密度同位元檢查碼的晶片。

Non-binary LDPC codes extended from binary LDPC codes have outstanding decoding performance and combat burst error. Recently, stochastic computation is a promising decoding method for non-binary LDPC codes. Although the previous stochastic works reduce the complexity by using symbol-serial representation of probability, the stochastic decoder for non-binary LDPC codes still has bottlenecks for VLSI implementation due to high computational complexity and huge storage requirements. In this thesis, three novel stochastic decoders: TFM-based, probability-RHS-based, and log-RHS-based are proposed. All of proposed decoders are synthesized in UMC 90-nm process with high area efficiency due to our improved architectures which have low computational complexity and less storage requirements. Finally, the log-RHS-based stochastic decoder for a (168, 84) regular-(2, 4) code over GF(16) is fabricated in chip with 3.75 mm2 core area including testing consideration and 96.6% chip density. According to the measurement results, this decoder can support a throughput of 1.32 Gb/s under 368 MHz clock frequency with 1014 k gate counts and its power consumption is 588 mW. Compared with the related state-of-the-art designs, this work has not only 2 times improvement in hardware efficiency but also 7 times improvement in energy efficiency. Moreover, to the best of our knowledge, this is the first chip of stochastic decoder for non-binary LDPC codes.