A 1.31Gb/s, 96.6% Utilization Stochastic Nonbinary LDPC Decoder for Small Cell Applications

Abstract

In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.