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dc.contributor.authorLi, Yimingen_US
dc.contributor.authorHwang, Chih-Hongen_US
dc.contributor.authorCheng, Hui-Wenen_US
dc.date.accessioned2014-12-08T15:17:22Z-
dc.date.available2014-12-08T15:17:22Z-
dc.date.issued2009-03-01en_US
dc.identifier.issn0167-9317en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.mee.2008.02.013en_US
dc.identifier.urihttp://hdl.handle.net/11536/12623-
dc.description.abstractImpact of the intrinsic fluctuations on device characteristics, such as the threshold voltage (V(th)) fluctuation is crucial in determining the behavior of nanoscale semiconductor devices. In this paper, the dependency of process-variation and random-dopant-induced V(th) fluctuation on the gate oxide thickness scaling in 16 nm metal-oxide-semiconductor field effect transistors (MOSFETs) is investigated. Fluctuations of the threshold voltage for the studied planar MOSFETs with equivalent oxide thicknesses (EOT) from 1.2 nm to 0.2 nm (e.g., SiO(2) for the 1.2 and 0.8 nm EOTs, Al(2)O(3) for the 0.4 nm EOT and HfO(2) for the 0.2 nm EOT) are then for the first time compared with the results of 16 nm bulk fin-typed filed effect transistors (FinFETs), which is one of the promising candidates for next generation semiconductor devices. An experimentally validated simulation is conducted to investigate the fluctuation property, Result of this study confirms the suppression of V(th) fluctuations with the gate oxide thickness scaling (using high-kappa dielectric). It is found that the immunity of the planar MOSFET against fluctuation suffers from nature of structural limitations. Bulk FinFETs alleviate the challenges of device's scaling and have potential in the nanoelectronics application. (C) 2008 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectThreshold voltage fluctuationen_US
dc.subjectRandom dopanten_US
dc.subjectProcess-variationen_US
dc.subjectGate-length deviationen_US
dc.subjectLine-edge roughnessen_US
dc.subjectModeling and simulationen_US
dc.titleProcess-variation- and random-dopants-induced threshold voltage fluctuations in nanoscale planar MOSFET and bulk FinFET devicesen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/j.mee.2008.02.013en_US
dc.identifier.journalMICROELECTRONIC ENGINEERINGen_US
dc.citation.volume86en_US
dc.citation.issue3en_US
dc.citation.spage277en_US
dc.citation.epage282en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000264743100014-
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