平面式與三閘極結構之N型無接面多晶矽薄膜電晶體的研製與分析

Abstract

在此篇論文當中，我們成功地研製平面式(planar)與具三閘(tri-gate)結構之N型無接面多晶矽薄膜電晶體(N-type junctionless poly-Si TFTs)，其薄膜是使用成熟的低壓氣相沉積系統(low pressure vapor deposition, LPCVD)製程與原位(in-situ)摻雜沉積而成，因此在整個元件當中，各部分都具有相當濃且均勻的摻雜分布，且所沉積的8至12奈米的無接面薄膜都非常的平坦且均勻。從元件電性的探討與比較上，我們可以發現所製作出的無接面電晶體比起以前傳統的反轉式(inversion mode)電晶體有著較為優越的輸出電流，這是由於無接面電晶體的通道內富含的大量載子以及大幅降低的串聯電阻所致。除此之外，不同結構參數如氧化層厚度與通道層厚度對電性的影響亦在此論文中深入討論。透過元件內部電容的量測，發現負的固定電荷(fixed charge)存在於二氧化矽與矽之介面附近，推測是因為大量磷原子的摻雜析出(dopant segregation)所導致。除此之外，因為無接面電晶體之傳導機制為塊材內部導通(bulk conduction)，因此驅動電流會與電流流經的面積成正比，通道內部傳輸電流也比較不會受到由表面而來的散射效應所影響。另外，在此論文也探討了溫度對無接面電晶體之效應，令人有趣的發現是平帶電壓(VFB)會恰巧等於零活化能(activation energy)的閘極電壓。 另一方面，考慮不同沉積系統對元件所帶來的影響，我們使用垂直式與水平式低壓氣相沉積系統製作無接面電晶體。經由元件電容的量測，我們發現前者比起後者的無接面電晶體擁有著較濃的載子摻雜濃度，因此也較易在二氧化矽及矽之間的介面產生摻雜析出的現象。除此之外，較濃的載子摻雜濃度也大幅地降低了串聯電阻，因此垂直式無接面電晶體擁有較高輸出電流。由於垂直式低壓氣相沉積系統提供較佳的薄膜結晶品質，所以製作的無接面電晶體有著較優越的電性如較陡直的次臨限擺幅(subthreshold swing)、較高的輸出電流、較小的遲滯窗(hysteresis window)。此外，我們在垂直式製作的電晶體中觀察到較佳的元件均勻性，這是由於垂直式低壓氣相沉積系統擁有良好的氣流設計、先進的升溫系統、與水平的晶圓擺放方式所致。 為了進一步探索無接面電晶體能應用於奈米領域的可行性，我們使用結合邊襯(sidewall spacer)與光阻薄化(photoresist trimming)的技術，製作了具100奈米線寬長度的平面式與三閘極式的無接面電晶體。由所得之實驗式的關係，我們可以由微縮通道長度精準地反向推判需要在光罩上設計的通道長度。在這如此短的通道長度的平面式無接面電晶體中，元件的電流與電阻的數據統計都能夠以通道長度的函數正確地做描述與比對。對於三閘極式無接面電晶體而言，狹窄的線圖形可以經由光阻薄化的技術精準地控制形成。除此之外，在極短奈米級的通道長度之下，於三閘極式的電晶體中窄化平面的通道寬度有助於提升抗拒短通道效應的能力。

In this dissertation, we had successfully fabricated and characterized n-type junctionless (JL) polycrystalline (poly-Si) thin-film transistors (TFTs) with either planar or tri-gated configuration. The proposed JL devices were fabricated with mature in-situ phosphorus doped process with low pressure chemical vapor deposition (LPCVD) capable of in-situ phosphorus doping process. The deposited poly-Si films thus feature heavy and uniform doping concentration in the whole device. Moreover, for the planar JL devices, the ultra-thin poly-Si channel with thickness less than 12 nm can be obtained with high uniformity and sharp interfaces. From the examination of the basic electrical properties, the fabricated JL device exhibits superior drive current to that of conventional inversion-mode (IM) devices, due to the abundant carriers contained in the channel which leads to the significant reduction of series resistance. Besides, impacts drawn from the structural parameters of JL devices such as channel thickness and oxide thickness were examined. Through the C-V characterization, the phosphorus dopant segregation is inferred to occur and responsible to the presence of negative fixed charges existing at the Si/SiO2 interface. Thanks to the bulk conduction in the JL device, the drive current is proportional to the cross-sectional area of the channel and less impact on the drive current is drawn from the scattering mechanisms occur at or near the surface. In addition, the effect of temperature is also investigated, and it is interestingly to find that the VFB is coincidentally equal to the gate voltage corresponding to activation energy about 0 eV. To further explore the effects drawn from different deposition equipment, the vertical and horizontal LPCVD have been used to fabricate the JL devices. Verified by the C-V characterization, it is found that the JL devices fabricated by vertical LPCVD, denoted as VJL devices, contains higher dopant (and thus carrier) concentration in the channel than that of JL devices fabricated by horizontal LPCVD, denoted as HJL devices, and has a higher tendency to induce dopant segregation at the Si/SiO2 interface. Furthermore, a higher carrier concentration also leads to a great reduction in series resistance, and hence improving the on-current in the VJL device. Besides, due to the better crystallinity fabricated by vertical LPCVD, the VJL device shows superior performance in terms of steeper subthreshold swing, higher on-current, and smaller hysteresis window. More importantly, better device uniformity is observed in VJL devices, which is ascribed to better gas flow design, advanced heating system, and horizontal wafer placement in the Vertical LPCVD. In order to explore the feasibility of JL devices in the application of nanometer technology, the planar and tri-gated JL device with 100 nm channel length was fabricated with a scheme which combines the sidewall spacer and photoresist trimming techniques. With the establishment of an empirical equation based on the experimental results obtained with the above scheme, the targeted nanometer-scale channel length can be well achieved with appropriately designed mask channel length. For the tri-gated JL devices, the width of the narrow line patterns can be well-controlled with the photoresist trimming method. With nanometer-scale channel length, the immunity of the tri-gated devices to the short channel effect is highly promoted.