用於非對稱式處理器系統之可同盟字元線快取記憶體以暫時性效能提升

Abstract

為降低現今嵌入式系統的能量消耗，非對稱式架構在現今嵌入系統中已為普遍的設計方式。該架構通常由兩種設計取向的處理器組成，一是追求高性能但較為耗電，另一為省電導向，即較有效率地使用能量。程式若交由非對稱式架構中較為省電的處理器(常為低電壓設計)來執行，整個系統的能量消耗將可進一步減低，因該處理器通常操作於低/超低電壓之下以達省電之目的。然而，傳統快取記憶體的效能及可靠度成為了系統下降電壓首先面臨的瓶頸。低電壓處理器的較差效能表現使得面臨部分的工作時必須叫醒高效能但較為耗電的處理器來執行。在本論文中，提出了基於同時驅動兩條word-line之可同盟字元線快取記憶體，藉以提供暫時性的性能提升和在低電壓下更高的可靠度。此外我們提供了快取記憶體同盟管理策略，使之在加速的過程當中不會因大量空間犧牲所造就過多能量代價。此可同盟快取記憶體可加速處理器並提高效能，使之能夠分攤高效能處理器之工作，進一步節省系統效能。本論文亦使用了用於感測器應用程式-EMD來評估整體非對稱式系統運行效能及能量消耗。

To lower the energy consumption of embedded systems, asymmetric architecture is commonly used in modern embedded systems. The asymmetric system is composed by two kinds of processors. One is for high performance and the other if for energy saving while providing enough performance. The energy of overall system can be saved by assigning task to be executed on energy saving core, which is usually applied in low-voltag (LV) or even ultra-low voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks the system performance in the LV/ULV environment. The poor performance of the low voltage core causes most of the workload need to wake up the host core and then be executed on the host core, restricting the limitation of energy saving. In this thesis, we propose a word-line alliable cache based on a ULV alliable 8T SRAM which has been widely used in low voltage operating environments that is able to perform reliable ultra-low voltage operation and provide the function of alliable word-lines. With the word-line alliable cache, the system is able to instantaneously speed up the LV/ULV core and to execute more applications. In our system-wide evaluation based on EMD real-workload on the sensor hub, the word-line alliable cache reduces approximately 36% of the energy consumption of the system.