應用於第四代行動通訊系統之多平行度混合基底前饋式快速傅立葉轉換處理器設計

Abstract

正交分頻多工(Orthogonal Frequency Division Multiplexing；OFDM)技術，近年來被廣泛應用於各式通訊系統中，例如：無線區域網路(Wireless Local Area Network；WLAN)、長期演進技術(Long Term Evolution；LTE)及第四代行動通訊系統(Long Term Evolution-Advanced；LTE-A)等等，而離散訊號傅立葉轉換(Discrete Fourier Transform；DFT)正是正交分頻多工技術之實踐方式。西元1965年，James W. Cooley和John W. Tukey發表了Cooley–Tukey algorithm ，即是現在廣為人知的快速傅立葉轉換 (Fast Fourier Transform；FFT) 演算法，該演算法大量減少了DFT運算所需要的運算與硬體複雜度，是OFDM/OFDMA調變通訊系統被大量採用的關鍵因素之一。 近年來，由於行動裝置的崛起、通訊系統規格及資料傳輸率的要求增加，FFT/IFFT處理器設計面臨更多挑戰，例如：功率消耗、面積複雜度、高倍平行度(Highly-parallel)、可重組式(Reconfigurable)設計、支援多重規格(Multi-standard)等。本論文針對第四代行動通訊系統中，下列各面向之FFT設計挑戰與問題，提出新的解決方案： (1) 針對硬體複雜度問題，提出可應用於非二的冪次方FFT之旋轉因子乘法方案與硬體架構，藉由Canonical Signed Digit (CSD) encoding及相同子運算式共享(Common sub-expression sharing)等技巧作架構設計，取代並解決傳統複數乘法器搭配唯讀記憶體(Read-Only Memory；ROM)所造成之高面積複雜度的問題。本旋轉因子乘法器可支援非二的冪次方點數之FFT運算且具有低面積、可管線化(Pipelined)、支援多重標準(Multi-standard)、可重組式(Reconfigurable)等好處，因此，也適用於各種通訊系統之FFT架構中。 (2) 提出前饋式Radix-3蝶形運算單元(Butterfly unit；BU)與多倍平行度2k×3點FFT架構設計方案，並將此技術結合改良型前饋式FFT處理器架構，提出一個可應用於第四代行動通訊系統之FFT處理器架構，此架構具有低面積、高吞吐率(Throughput rate)、可重組(Reconfigurable)等優點。

The multi-carrier modulation method called OFDM (Orthogonal Frequency Division Multiplexing) [1], for examples: WLAN (Wireless Local Area Network) ,LTE (Long Term Evolution) and forth generation (4G) communication system (LTE-A). And DFT (Discrete Fourier Transform) is the most critical component in implementing an OFDM system. In 1965, JW Cooley and John Tukey published the Cooley-Tukey algorithm , which is well known as FFT (Fast Fourier Transform) algorithm. This algorithm significantly reduces the computational complexity and hardware cost required for DFT operation and becomes one of the key reasons why OFDM/OFDMA modulation can be widely used with relatively low complexity. Since recent years, as a result of increasing requirements of mobile devices, particularly the data transmission rate, FFT/IFFT processor design has become more and more challenging, The concerned important design issues include power consumption, area complexity, throughput, reconfigurable design and multi-standard supporting. This thesis presents several FFT design challenges in the fourth-generation mobile communications systems and corresponding solutions as follows: In order to reduce the hardware complexity of FFT processor, this thesis proposes a novel ROM-less twiddle factor multiplication scheme and architecture that can be used in non-power-of-two FFT processor. With the help of techniques such as CSD (Canonical Signed Digit) encoding and Sub-expression sharing, high area complexity problem occurred in conventional complex multiplier plus ROM design is solved with proposed rotator. The rotator design method has the advantage of supporting multi-standard OFDM systems, it is reconfigurable and can be applied to any other FFT processor. A feedforward Radix-3 BU (Butterfly Unit) and parallel 2k×3-point FFT architecture are presented. Those design methods are applied to the FFT processors for 4G communication system so as to achieve the goal of low-area complexity, high parallelism and high throughput rate.