標題: | 運用非同步電路設計之快速傅立葉轉換處理器 The Design of Asynchronous FFT Processor |
作者: | 劉建春 Liu, Jian-Chun 陳昌居 Chen, Chang-Jiu 資訊學院資訊學程 |
關鍵字: | 非同步電路;快速傅立葉轉換;雙軌;Asynchronous;FFT;4-phase;dual-rail |
公開日期: | 2008 |
摘要: | 快速傅立葉轉換處理器(FFT Processor)應用在非常多的領域,例如正交分頻多工 Orthogonal Frequency-Division Multiplexing(OFDM)系統、數位訊號處理Digital Signal Process(DSP)模組、網路資料傳輸(WLAN、xDSL、WiMAX、Wireless)、數位影像處理(Image Processing Technique)、高畫質電視地面廣播High-Definition Television(HDTV)、MP3編碼器/解碼器(Encoder/Decoder)、頻譜分析(Spectrum Analysis) ...等等。
在這篇論文裡,我們運用非同步電路設計的方式,來簡化傳統同步電路傅立葉轉換處理器的設計;去除在同步電路設計時,需考慮時脈偏斜(clock-skew)、時脈分佈以及時脈頻率最壞情況估算的煩惱;盡量減少乘法運算、並以非同步管線之控制電路來增加效能。用此方式設計,在電壓、溫度以及運行處理參數上,具有較佳的環境抗逆性。 The Fast Fourier Transform (FFT) Processor has been widely applied for many applications, such as Orthogonal Frequency-Division Multiplexing (OFDM) Systems, Digital Signal Process (DSP) modules, Network Data Transmission (WLAN, xDSL, WiMAX, Wireless), Imaging Processing Technique, High-Definition Television (HDTV), MP3 Encoder/Decoder and Spectrum Analysis … etc. In this thesis, we apply the design of asynchronous circuit to simplify the conventional synchronous circuit of FFT processor. It stays away from worries that caused by clock-skew, clock-distribution and clock-rate worst-case estimation of synchronous circuit design It also reduce the computation of multiplier, and improve the performance by asynchronous pipeline control circuit. This design is tolerant to variations in supply voltage, temperature and fabrication process parameters. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079679505 http://hdl.handle.net/11536/44059 |
顯示於類別: | 畢業論文 |