以非同步電路實作之無死結環面網路晶片的路由器設計

Abstract

NoC 在近年來變成是一門十分熱門的題目，因為它可以用來降低設計的複雜度和增加處理單元 (PE) 的重複使用地可能性。使用NoC可以有效的支援將多個處理單元 (PE) 整合到同一個晶片的連結方法。 在這一篇論文中，我們使用非同步四象雙軌（four phase dual rail）的編碼方式去實作一個 NoC 上的路由器。同時，我們使用雙向的 Torus 建立 NoC 上的連結網路。我們也自行定義在此網路上所傳輸的封包格式和路由器對網路介面間傳輸的封包格式。最後，我們將此 NoC 架構和多個處理器組合並應用，來確保我們的架構在 MPSoC 下的實用性。

In recent years, NOC (Network on Chip) becomes a famous topic. For reduce the design complexity and increase the reuse ability of the PEs (processing elements). NOC (Network on Chip) has been proposed to support the integration of multiple PEs (processing elements) in a single chip. In this thesis, we implement an asynchronous router for NOC (Network on Chip) which uses the four phase signaling with dual rail encoding. And we use the bi-direction Torus to build the interconnection network. We also present packet format we defined that be used to network interface level and routing level. Finally, we also present our router for a NoC (Network on Chip) based multiprocessor, to prove that our implementation is useful in MPSoC (multiprocessor system on chip).