標題: | Self-Timed Torus Network with 1-of-5 Encoding |
作者: | Chang, Yuan-Teng Huang, Man-Chen Cheng, Wei-Min Tsai, Hung-Yue Chen, Chang-Jiu Cheng, Fu-Chiung Chu, Yuan-Hua 資訊工程學系 Department of Computer Science |
關鍵字: | muitcore;asynchronous circuit;torus;VLSI;SoC;interconnection network |
公開日期: | 2009 |
摘要: | Nowadays, MPSoCs or multicore processors have been becoming the major trend of system or processor designs. Thus the design of interconnection networks becomes the most important issue of all. However, lots of different problems may arise in the network design and they should be carefully handled. It is widely known that most of these problems can be resolved easily by asynchronous circuits. But because of the difficulties of implementation, still only some real implementations of asynchronous networks. In this paper, we implemented a self-timed torus network with 1-of-5 DI encoding. The design was implemented in gate-level with Verilog HDL and synthesized with TSMC 0.13 mu m technology. The simulation shows that the network can operate correctly in 63.9 MHz. |
URI: | http://hdl.handle.net/11536/16566 |
ISBN: | 978-1-4244-2975-2 |
期刊: | ISCE: 2009 IEEE 13TH INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS, VOLS 1 AND 2 |
起始頁: | 325 |
結束頁: | 328 |
顯示於類別: | 會議論文 |