Self-Timed Torus Network with 1-of-5 Encoding

Abstract

Nowadays, MPSoCs or multicore processors have been becoming the major trend of system or processor designs. Thus the design of interconnection networks becomes the most important issue of all. However, lots of different problems may arise in the network design and they should be carefully handled. It is widely known that most of these problems can be resolved easily by asynchronous circuits. But because of the difficulties of implementation, still only some real implementations of asynchronous networks. In this paper, we implemented a self-timed torus network with 1-of-5 DI encoding. The design was implemented in gate-level with Verilog HDL and synthesized with TSMC 0.13 mu m technology. The simulation shows that the network can operate correctly in 63.9 MHz.