三維快閃記憶體技術及其特殊現象之研究

Abstract

三維快閃記憶體將取代傳統的平面快閃記憶體成為下一世代快閃記憶體的技術主流，而驅動此一技術演變的主要動力來自三維快閃記憶體可持續降低快閃記憶體的單位位元成本。在三維快閃記憶體的技術發展歷史上，第一代三維快閃記憶體因冗長的生產流程而不符合經濟效益，每一層記憶體的製作都是獨立互不相關。第二代的三維快閃記憶體改採用所謂的”多層堆疊一次蝕刻”的概念，並建立了三維快閃記憶體的里程碑。其中最具代表性的就是由東芝所發表的 Bit-Cost Scalable technology (BiCS)。此技術是先將許多層的記憶體做垂直堆疊，再利用一次性的蝕刻將不同層的記憶體做蝕刻而自動形成層層分離的三維快閃記憶體。在此技術發表後，許多不同的三維記憶體結構都陸續推出且已有產品在市面上販售。 在三維記憶體的發展上，每一種架構都有其優缺點，如何做一個有系統性的分析是很值得研究的。在本論文的第二章中，藉由定義好的水平與垂直間距(pitch)並利用模擬軟體可做一有系統性的比較。從研究中發現，採用水平電流流動方式的架構，如垂直閘極結構 (vertical gate)，除可在記憶體的層數堆疊上具有優勢外其架構也較易微縮。反之，使用垂直電流流動方式的架構，將遭遇到電流衰退的問題，且水平間距的微縮極限約略在50奈米左右。 第三章將透過模擬軟體詳細介紹如何改善元件特性最差的三維記憶體技術。在這些架構中，特性最差的是Vertical Stack Array Transistor (VSAT) 架構。該架構不論是在電流走向或是閘極控制上的表現都不及其他架構。為了改善其缺點，額外的字元線 (word line)分離法首先被提出，該法藉由分離閘極控制左右兩側的電流通到，除可改善元件特性外，也大幅改善了位元單位密度。此外上下輔助閘極可有效改善電流衰退問題。 前面提到多晶矽通道將取代單晶矽通道成為電流流通的通道，此法雖然可以提供較大的製程彈性，但任意分怖的結晶邊界(grain boundary)與結晶邊界缺陷(grain boundary trap)將使電性衰退。第四章將實驗並搭配模擬軟體來研究此一現象，模擬軟體可先提供任意分佈的結晶邊界與結晶邊界缺限環境並研究其對電性的影響。從模擬與實驗的研究結果中發現，當缺陷越多，元件特性衰退越嚴重。此外，利用此方法可以研究多晶矽電晶體所獨有drain induced grain barrier lowering(DIGBL)與gate induced grain barrier lowering (GIGBL)現象。並利用DIGBL現象將電壓分別加在汲極或源極，可檢測出主要影響元件特性的結晶邊界缺限位置與其數量。 三維記憶體的另一個特殊現象就是通行閘極電壓干擾( pass gate voltage interference)。在三維記憶體的製作過程中，要製作有掺雜載子濃度的接面在字元線與字元線間有其難度。利用外加電壓在臨近的字元線上以產生邊緣場效應(Fringing Field)，邊緣場效應可產生虛擬的接面而使得電子可以從源極流到汲極。 但此邊緣場效應不僅僅會在字元線間產生虛擬的接面，同時也會穿透到元件的通道並對元件電性造成影響，此效應將隨元件的微縮而更形嚴重。第五章將針對此一現象作一詳盡的探討。 最後，在本論文中，我們將先針對已發表的三維快閃記憶體做一廣泛性的研究與探討，並且對有電性缺陷的三維快閃記憶體做研究與改進。在基礎研究上，任意分佈的結晶邊界與其缺陷也將一併探討。為了在三維快閃記憶體內形成虛擬接面，通行閘極電壓所形成邊源場效應造成的干擾也將被探討。最後，藉由此研究過程將更加了解三維快閃記憶體的發展與未來。

3D NAND Flash architecture will replace the traditional planar NAND Flash as the mainstream of the next generation NAND Flash technology. The drive force to develop 3D NAND Flash technology is the continuing cost down per bit by increasing the memory layers stacking. In the technology development history of 3D NAND Flash, the first generation 3D NAND Flash architecture is not economic because of its copious process flow in fabricating each memory layer. Then, the concept, Multiple Layers Stack and One Critical Cut, creates the milestone in the secondary generation. The representative technology is Bit-Cost Scalable technology (BiCS). In this generation, the multiple memory layers are stacked vertically and one critical etch process formats each memory cell separately. Henceforward, plenty of 3D NAND Flash architectures are proposed and some of them are mature enough to manufacture the NAND Flash products. Since each 3D NAND Flash technology has its specific merits and demerits, a systematic analysis is investigated in Chapter 2. The fair comparison is done with the well definition of the horizontal and vertical pitches by using TCAD simulator. It also analyzes the merits and demerit among 3D NAND architectures in detail. The horizontal current flow approach such as Vertical Gate (VG) architecture has its benefit in the memory layers stacking and the horizontal pitch scaling while the vertical current flow approach suffers the current degradation and the pitch scaling limitation beyond 50nm. The worst case in these 3D NAND architectures is the Vertical Stack Array Transistor (VSAT) technology. The multiple U-turn current flow and single gate structure perform the worst cell characteristic. To improve its disadvantages, the asymmetrical WL cut process and the top and bottom assisted gate approaches are proposed. These processes will be introduced in Chapter 3. From the simulation results, not only the bit density is improved by applying the asymmetrical WL cut process but the cell performance becomes better with the aid of the assisted gate structure. In 3D NAND architectures, poly-Si material replaces the crystal silicon as the conduct channel material. Though this approach provides the process flexibility, the electrical characteristic degrades due to the randomly distributed grain boundaries and grain boundary traps. In Chapter 4, TCAD simulator is applied to create the environment about the randomly distributed grain boundaries with its corresponding traps. By comparing the experimental and simulation results, the cell performance degrades severely with the heavier grain boundary conditions. Drain induced grain barrier lowering (DIGBL) effect and gate induced grain barrier lowering (GIGBL) effect are two specific phenomena in the poly-Si thin-film transistor. In the application of the DIGBL effect, the decisive grain boundary location with its traps can be examined by applying the read voltage at the drain side or source side. This method can be applied to locate the main grain boundary barrier. Another specific phenomenon in 3D NAND Flash technology is pass gate voltage interference (Vpass interference). In the 3D NAND Flash process integration, it is not easy to form the doped junction between WLs and the junction-free structure is naturally formatted. To read through the selected memory cell, the suitable pass gate voltage is applied in the WLs’ except the selected one. The fringing field from the adjacent WL forms the virtual junction under the space region and the electrons can flow from source to drain. However, this fringing field also penetrates into the selected WL to affect its cell performance. This situation becomes worse with the pitch scaling. This topic will be studied by comparing the experimental and simulation results in Chapter 5. In this dissertation, a general overview to understand 3D NAND Flash technology development is obtained at first. The imperfect 3D NAND Flash technology is studied extensively and improved significantly. In the fundamental study, the impact of the randomly distributed grain boundary and its traps are studied in detail. Pass gate voltage forms the virtual junction inside NAND Flash, but the fringing field also induces the Vpass interference. After evaluating them, an in-depth understanding in 3D NAND Flash is obtained. Several future works will be also introduced in Chapter 6.