一種改善多顆粒MLC NAND快閃記憶體寫入速度的方法

Abstract

近年來，NAND快閃記憶體被大量運用在各種儲存裝置上，其容量、速度不斷在提升，但NAND快閃記憶體的寫入速度一直是一個棘手的問題。為了改善NAND快閃記憶體的寫入速度，一般會使用NAND快閃記憶體內建的快取寫入(cache program)和多平面(multi-plane)功能，以及在單一通道上使用多顆NAND快閃記憶體以交錯寫入(write interleaving)來疊加其寫入的速度。基於MLC NAND快閃記憶體的特性，寫入的時間有長有短，使得交錯寫入的效果在一定數量上的裝置時效果不如預期。本論文提出更改寫入順序的方法來提升交錯寫入的效果，由於此方法只有更改寫入的順序，不會與任何的演算法有衝突，可以運用在各種演算法之中，都會對寫入的速度有所提升，而且不會增加任何硬體上的成本。以實驗結果顯示約可增加10%左右的寫入速度，但實際套用到不同的產品時會依產品的規格有些許差距。

The NAND flash memory is popular in modern mass storage devices. Their capacity and performance keeps improving with the aid of the advanced process. However, the writing speed of the NAND flash memory is the bottleneck of high-capacity NAND flash memory. To improve the writing speed of NAND flash memory, it is common to use the built-in functions of the NAND flash memory such as the cache program functions and multi-plane functions, and to apply the interleaved writing scheme to the multi-chip NAND flash memory with single communication channel. However, the writing speed of the multi-level cell (MLC) NAND flash memory with the help of all the techniques is still limited due to the characteristics of the MLC NAND cells. The main issue is the programming time of the MLC NAND flash memory varies from page to page. It lowers down the interleaved writing efficiency than theoretical expectation. This thesis presents a method by reordering the programming sequence to improve the efficiency of write interleaving with multiple chips of MLC NAND flash memory. Because the proposed method only reorders the programming sequence, it does not conflict with any NAND flash translation algorithm. As a result, this method can be adopted no matter what translation algorithm is used and improves the writing performance without any hardware overhead. According our experimental results, the writing speed is improved by around 10%. The improvement depends on the characteristics of MLC products.