非揮發性快閃記憶體新式寫入序列方法之研究

Abstract

由於過去幾十年來NAND型快閃記憶體生產成本的持續下降，NAND快閃記憶體已被廣泛的使用在目前各式的消費型電子產品中。因為它採用串聯的架構，NAND型快閃記憶體相當適合製程上的微縮，此外每個記憶體單元可儲存的資訊量還可達到四個位元的大小(多位準型單元)。除了可以提供高集成密度的記憶容量之外，它還有極佳的耐沖電阻(Shock Resistance)及低功率損耗的特性。 不過NAND快閃記憶體也有幾個常見的缺點，如高位元錯誤率(Bit Error Rate) 還有為了維持產量而容易在製造過程中產生壞軌區(Bad Blocks)，以及較差的重複使用率。 在原本NAND型快閃記憶體的架構中，寫入及抹除的過程是採用福勒-諾德漢穿隧效應(Fowler-Nordheim tunneling)來達成。採用此種架構，我們可以有較小的寫入電流，但是所需偏壓卻相當高(高達二十伏特)，因此，對於接面處的氧化層會造成相當的傷害，進而造成元件可靠度與性能的下降。

在此篇論文中，我們提出了一種新穎的寫入序列架構，不但維持了低功率損耗的特性也降低了使用偏壓的位準。我們使用了三維的數值模擬與實際的量測來分析，使用的樣品為46奈米製程的記憶體陣列。根據我們的研究成果，我們成功降低了三倍以上的寫入電場，另外我們亦分析了新舊方法之寫入速度、臨限電壓分布與各種不同寫入雜訊的特性比較。

Due to its continuous cost reduction through last several decades, NAND Flash has been widely adopted in consumer electronics. NAND Flash is well-suited for scaling due to its unique cell-in-series architecture; moreover, each cell can store up to 4bits of information (Multi Level Cell array). Aside offering the ultra-high-density storage capacity, this memory possesses excellent shock resistance and is characterized with lower-power operation. Disadvantages of the NAND Flash include high bit error rate, presence of number of the bad blocks due to manufacturing yield constraints and chip wearing over the time. In the several years after architecture emerged, Fowler-Nordheim tunneling has been utilized to program and erase NAND Flash cell. While consuming a low program string current, it requires very high voltages (up to 20V), causing a large stress to interface oxide, degrading the device reliability and performance. In this work the novel low-voltage low-power NAND Flash programming sequence is presented. Study was carried out with the help of 3D numerical simulations and in situ measurements. The research workbench included the 46nm-node 128 BL 32bit string mini-array. As result of this research, programming stress reduction up to 3 times was achieved. Programming speed, memory window and various types of program disturb were investigated and compared against the traditional program operation.