氮化矽側壁硬式光罩製造之環繞式閘極多晶矽無接面奈米線薄膜電晶體特性研究

Abstract

在本篇論文中，成功利用氮化矽側壁硬式光罩(nitride-spacer hard mask)的方式，僅藉由I-Line微影技術即可有效製作高度微縮之電晶體，其中通道長度可微縮至200奈米以下，並可達到15奈米的奈米線(nanowire)寬度。本文並使用同步摻雜之低壓化學氣相沉積形成多晶矽無接面電晶體之高摻雜濃度通道。由於環繞式閘極(Gate-All-Around)的形成，可由低於100 mV/dec的次臨界擺幅顯示出良好的閘極控制能力。另外，本文中亦利用Pelgrom Plot來探討臨界電壓之變異。在有效微縮的元件中，可量得清晰的二層級隨機電報雜訊(2-level random telegraph noise)並進行分析。我們並由量測之信號萃取不同偏壓條件下的特性常數，包含在數毫秒範圍變化的時間常數，以及萃取之隨機電報雜訊振幅，得以清楚研究二層級隨機電報雜訊的行為。

In this thesis, effectively scaled poly-Si nanowire (NW) junctionless (JL) devices were formed by nitride hard mask methods simply with I-Line lithography. In the fabrication, in-situ doped poly-Si deposited by LPCVD is adopted to serve as the heavily-doped channel of JL devices. Devices with channel length shorter than 200 nm and NW width around 15 nm have been successfully fabricated. The steep SS lower than 100 mV/dec is achieved owing to the good gate controllability by the gate-all-around structure. The Pelgrom plots are made to analyze and discuss the threshold voltage fluctuation. We also observe clear 2-level RTN characteristics in our scaled devices. RTN time constants are extracted to be around a few milliseconds, and dId/Id are analyzed to probe the switching properties between discrete levels at different bias conditions.