針對異質多核心系統之高效率資料傳輸與管理機制

Abstract

異質多核心系統架構目前被廣泛應用在許多高效能運算或講究功耗效率的運算系統中。在此異質系統中，通常包含傳統的純量處理器，以及支援大規模平行運算的通量處理器。不同類型處理器利用自身架構的優勢，負責執行不同類型的資料處理，進而使整體運算能達到更高的效益。在運算的過程中，資料會在系統內的異質核心之間傳輸，以利不同核心對資料作有效的處理。前人的研究顯示，在異質多核心系統內的資料傳輸與使用，是影響整體系統效能的重要因素之一。 此外，不同於純量處理器，通量處理器在執行大規模平行運算時，傾向將使用到的資料放在鄰近處，以便一次取得，此機制稱為資料聯合存取（Coalescing）。針對上述異質多核心系統中的資料傳輸與管理議題，本篇論文提出一機制使資料在運算期間同時傳輸資料，以減少資料傳輸時的等待時間。另外，本論文亦提出一追蹤資料使用模式之硬體架構，針對通量處理器的資料位置作重新的排序，改善其資料聯合存取行為，減少記憶體存取次數，進而增進其整體運算效能與本地記憶體資料使用效率。當通量處理器支援的平行度較高時，所提出的資料追蹤硬體架構能提供的好處也會越高。本篇論文的實驗顯示，所提出的同時傳輸架構可有效的隱藏資料傳輸的延遲，並增加47%的執行效能，所提出的資料追蹤機制，最高能減少通量處理器中75%的記憶體存取次數。

Heterogeneous many-core systems are widely adopted in execution system aiming at high performance computing and energy efficiency nowadays. A heterogeneous system consists of traditional scalar processors and throughput processors support a large quantity of parallel executions. Different type of processors are in charge of processing distinct data executions according to the benefit of their own architecture. During the executions, data will be transferred between the heterogeneous cores in order to elaborate the advantages of different cores to process the data more efficiently. According to the previous research, the data transfer and management in heterogeneous many-core system are the important factors influencing the overall performance. Furthermore, in contrast to scalar processor, the throughput processors intend to allocate the data to the adjacent place as doing high quantity parallel executions, and it is called data coalescing. For the data transfer and management issues of heterogeneous many-core system, this thesis proposes a scheme to do the asynchronous transfer to eliminate the waiting time of data transfer. Also, this thesis propose a hardware architecture to track the data access pattern and reallocate the data position for throughput processors. It could ameliorate the data coalescing and reduce the number of memory transactions and then improve the overall performance and memory usage efficiency. The proposed hardware tracking architecture will get more benefits when the parallelism is higher with the throughput processors. The experiments of this thesis show the proposed asynchronous transfer could hide the transfer latency and get 47% improvement and the proposed data tracking mechanism could reduce the 75% number of memory transactions.