側壁蝕刻與非合金歐姆接觸之增強型砷化銦通道高電子遷移率電晶體應用於高頻與低耗能邏輯元件之特性評估

Abstract

為了延續摩爾定律，其關鍵在於如何使元件在漏電流不增加的情況下，使導通電流最大化。一般相較於矽而言，三五族半導體有較高的載子遷移率且其基板具有半絕緣特性，這些材料性質結合能帶設計、磊晶成長設計和不同的製程能夠提升元件特性。近年來，由於三五族砷化銦鎵材料的高電子遷移率以及高電子遷移率電晶體的二維電子氣，高銦含量的砷化銦鎵通道高電子遷移率電晶體已在高速度及低耗能邏輯應用方面展現極大潛力。 在此研究中，成功的製作了一百奈米閘極線寬的砷化銦通道高電子遷移率電晶體，並且透過先進的側壁蝕刻技術、非合金歐姆接觸技術、二次閘極蝕刻以及白金閘極掘入技術，使元件展現優異的高頻特性。此研究比較了在低操作偏壓下(VDS=0.5V)使用此先進製程技術的砷化銦通道量子井場效電晶體與未使用此製程的元件，發現透過這些先進製程步驟，使元件有展現更高的崩潰電壓、更高的轉導值、較佳飽和電流、較低的次臨界擺幅、較小的汲極能障降低，以及較高的電流增益截止頻率 (可達到489GHz) 和非常短的閘極延遲時間。由這些特性可以得知，一百奈米的砷化銦量子井場效電晶體是適用於高增益、以及低操作偏壓的高頻元件應用。 本文的最後，另外針對一百奈米砷化銦高電子遷移率電晶體於未來高速邏輯電晶體運用做評估，發現在低偏壓下(VDS=0.5V)元件展現相當優異的邏輯特性，包括其汲極能障降低是相當低的50mV/V，而次臨界擺幅也是相當低的63.3mV/decade，此外，此元件的閘極延遲時間低於0.32 p sec，此外，其開關電流比值大於1.3×104。這些研究結果可以證實一百奈米增益型砷化銦通道量子井高電子遷移率電晶體極有潛力作為未來高速邏輯電晶體的使用。

In order to extend Moore’s law. The key point lies in maximizing the device on-current, while suppressing the leakage currents. In general, III-V compound semiconductors have significantly higher intrinsic mobility than silicon and the substrates are semi-insulating. These material properties combine with band gap engineering, epitaxial layer growth technique and process technologies result in devices with excellent performance. Recently, High indium content InGaAs-based HEMTs are particularly promising for future high-speed and ultra-low power logic application because the excellent electrical properties of InxGa1-xAs material and the superior band-gap design of HEMTs. In this study, the 100 nm InAs HEMTs processed with sidewall etch process, Ti/Pt/Au non-alloyed ohmic process, two-step recess and Pt gate sinking technologies for RF applications were fabricated. Depletion and Enhancement Mode InAs Channel HEMTs of the developed 100 nm InAs HEMTs with these advanced processes exhibit better performance than the conventional InAs HEMTs at low applied voltage such as better current saturation, lower output conductance (go), smaller negative threshold-voltage (VT), higher current-gain cut-off frequency (fT) of 489 GHz. The excellent electronic performances indicate the developed 100 nm InAs HEMTs are suitable for high-gain, low noise and low voltage applications. In addition to high frequency RF applications, the evaluations of 100 nm InAs thin channel HEMTs for high-speed logic applications have also been demonstrated in this study. The devices show outstanding logic performance in low applied voltage (VDS=0.5 V). The drain induced barrier lowering (DIBL) is 50 mV/V, subthreshold swing (SS) is 63.3 mV/decade, and intrinsic gate delay (CV/ION) is less than 0.32 psec, and ION/IOFF higher than 1.3 × 104. These results demonstrate that the E-mode InAs HEMTs have great potential for future high-speed and low-power logic application.