一款應用於可程式化實驗室晶片之以取比例為基礎的高精準度及高效率電容讀出電路

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	康艾文	en_US
dc.contributor.author	KARSTEN, IVAN	en_US
dc.contributor.author	李鎮宜	en_US
dc.contributor.author	Lee, Chen-Yi	en_US
dc.date.accessioned	2015-11-26T01:02:14Z	-
dc.date.available	2015-11-26T01:02:14Z	-
dc.date.issued	2015	en_US
dc.identifier.uri	http://140.113.39.130/cdrfb3/record/nctu/#GT070260819	en_US
dc.identifier.uri	http://hdl.handle.net/11536/127274	-
dc.language.iso	en_US	en_US
dc.subject	電容讀出電路	zh_TW
dc.subject	之以取比例為基礎	zh_TW
dc.subject	Capacitive Readout Circuit	en_US
dc.subject	Proportion-based	en_US
dc.title	一款應用於可程式化實驗室晶片之以取比例為基礎的高精準度及高效率電容讀出電路	zh_TW
dc.title	High-Resolution and High-Efficiency Proportion-Based Capacitive Readout Circuit for Field Programmable Lab-On-a-Chip (FPLOC) Application	en_US
dc.type	Thesis	en_US
dc.contributor.department	電機資訊國際學程	zh_TW
顯示於類別：	畢業論文