砷化銦/砷化鎵量子點紅外線偵測器陣列之低溫互補式金氧半讀出積體電路設計與分析

Abstract

本論文提出並分析低溫(Cryogenic)互補式金氧半(CMOS)讀出電路設計以製作運用在砷化銦/砷化鎵量子點紅外線偵測器陣列光訊號讀出之積體電路晶片。讀出電路為紅外線影像系統中偵測器陣列與後級訊號處理間的重要介面電路。為運用矽半導體元件電路之優良特性與匹配紅外線偵測器材質之低溫工作環境，我們提出了可工作在低溫環境下之讀出電路架構，並以互補式金氧半製程技術完成電路的設計、模擬、與晶片研製。而所製作之讀出晶片中的優異效能與成果均已由實驗或模擬驗證。 利用『緩衝式閘調變輸入』(Buffered Gate Modulation Input)讀出架構，可以改進傳統『閘調變輸入』(Gate Modulation Input)的問題與缺點，並完成包括適應性增益控制(adaptive gain control)與電流式背景壓抑(current-mode background suppression)功能的讀出晶片。此前級訊號處理功能(on-FPA signal processing)可以提高讀出電路的效能並降低後級電路雜訊之影響。電流式背景壓抑更可提高訊號動態範圍與避免積分電容飽和。雙重三角取樣(Double Delta Sampling)電路也被使用來減少固定樣式雜訊(fixed pattern noise)、時脈回饋雜訊和通道電荷注入。一實驗性16x16讀出晶片使用0.35 μm 2P4M N-well互補式金氧半技術設計並完成晶片研製，在77K溫度下及3.3 V工作電壓，其量測結果成功驗證了讀出晶片的效能。輸出線性度為95%、最大輸出擺幅為1V、最大讀出速度為1.25 MHz、畫面速率為4880 frames/sec、功率消耗為 30 mW。此高效能讀出電路具有高注入效率(injection efficiency)、高動態範圍(dynamic range)、高電荷容量(storage capacity)、低雜訊等優點，可適用於大範圍背景亮度與高對比影像讀出的運用。 我們深信，吾人所提出之互補式金氧半讀出電路架構以及其設計技術已為紅外線影像系統之讀出處理電路設計提供一個新方向。爾後，相關的研究發展與實際應用於不同影像系統包括可見光與紅外線將持續進行。

In this thesis, a cryogenic CMOS readout structure is proposed, developed, and applied to the implementation of photon signal readout integrated circuit for InAs/GaAs quantum-dot infrared detector array. The silicon readout circuit is an important interface circuit of detector array and signal processing stage in the IR image system. To achieve high performance readout and fit the cryogenic working characteristic of IR detector material, a cryogenic CMOS readout structure has been developed and fabricated. The functions and superior readout performance of the proposed CMOS readout structure have been verified by experimental measurement under 77K environment or simulations. By using the buffered gate modulation input (BGMI) circuit, it can improve the performance and problem of the conventional gate modulation input (GMI) with adaptive gain control and current-mode background suppression. The on-FPA signal processing capability of BGMI circuit at front stage can reduce the noise effect of downstream circuit and improve the readout performance. The current-mode background suppression can increase the signal dynamic range and avoid integrating saturation on capacitor. Moreover, the double delta sampling (DDS) circuit is used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental 16x16 readout chip has been designed and fabricated by using 0.35 μm 2P4M N-well CMOS technology. The measurement results of the fabricated readout chip under 77K and 3.3 V supply voltage have successfully verified both readout function and performance. It is shown that the linearity performance of the readout chip is better than 95% and the maximum output swing is 1V. The maximum readout speed is 1.25 MHz. The frame rate is 4880 frames/sec. The total active chip power is below 30 mW at 77K. It is shown that a high-performance readout interface circuit for IR FPA with high injection efficiency, high charge sensitivity, high dynamic range, large storage capacity, and low noise is realized. These advantageous traits make the readout circuit suitable for the various applications with a wide range of background. It is believed that the proposed CMOS readout circuit and the associated design methodology offer new design scope and future feasibility for new-generation readout ICs of infrared detector array. Further improvement on circuit performance and practical applications in various image system including visible and thermal image readout will be explored and developed in the future.