雙介電層低功耗電阻式記憶體之設計與最佳化

Abstract

傳統非揮發性記憶體如FLASH 和SONOS 等快閃記憶體有許多先天上難以克服的缺點，如高的操作電壓、漏電(charge loss)和寫抹不匹配(Mismatch between Program and Erase)，穿隧氧化層厚度也阻礙了元件的微縮。為了解決這些的問題，電阻式記憶體近年來成為非揮發性記憶體的熱門主題，乃因其擁有高密度、低成本、結構簡單、製程容易及具有極佳的微縮特性等優點。至於電阻式記憶體的氧化物材料有很多選擇，像是三氧化二鋁、氧化鎳、二氧化鉿等。另外，在電極材料上也有許多不同的選擇，例如白金、鎳、氮氧化鈦、鎢等。在本論文中，吾人將製作以氮氧化鉿、二氧化鉿和三氧化二鋁為基底之電阻式記憶體，並且比較不同的下電極材料對元件特性的影響。

首先，我們比較不同介電層厚度對元件的影響，並選出特性最好的介電層厚度條件來進行進一步的研究。而在退火方面，我們嘗試了不同的溫度及不同的時間，並從中選取出最適合的條件。另外，也探討不同下電極材料對於電阻式記憶體特性的影響，最後，並且提出改善的方法。

其次，我們在國家奈米元件實驗室透過黃光的製程，製作出的小 面積立體結構的電阻式記憶體元件，且透過量測不同的大小元件的電性得知其對於電阻式記憶體元件特性的影響，而且這批元件在耐久度(endurance)及100℃下的保存度(retention)測試都獲得良好的成果，並且在耐久度的測試上我們也發現元件面積越小會使得電阻的變化量會越小。 目前，最熱門的電阻式記憶體架構是所謂的交叉堆疊式(crossbar)。但是若直接將電阻式記憶體接成縱橫的架構，則會有很嚴重的潛洩電流(sneak current)，為了抑制潛洩電流，我們一般都會將電阻式記憶體與另一個元件相連，在往後我們會將我們的電阻式記憶體與電晶體連接成1T1R的結構來進行操作，透過增加一個電晶體，我們可以確保元件在未被操作時的電阻都是處在高組態的狀態，因此可以成功的抑制潛洩電流。另外，透過控制電晶體閘極電壓的大小，我們則不需要再透過量測儀器來限定電阻式記憶體在操作時的限制電流。

Charge-trapping memory devices (e.g., FLASH, SONOS etc.) have several inherent disadvantages that are difficult to overcome, such as higher operating voltage, charge loss, and mismatch between program and erase. The thickness of tunnel oxide also limits the device scaling. In order to solve these problems, Resistance-change Random Access Memory (RRAM) has recently received much more attention as a result of high-density, low-cost, simple structure (Metal-Insulator-Metal), easy fabrication, and excellent potential of scaling. As to the oxide materials, there are many choices such as Al2O3, NiO, HfO2 etc., in addition, there are many choices in the material of bottom electrode such as Pt, Ni, TiN, W etc. In this thesis, we will prepare HfON/HfO2/Al2O3-based RRAM with different bottom electrodes and study the optimization of the device materials and electrodes.

First, we examine the effect of different thickness dielectric layer and choose a better condition of dielectric thickness to do the further study. As to the effect of annealing, three different temperature and time were used to anneal the prepared devices. Besides we also investigate the effect on the different materials of bottom electrode and proposed the way to achieve better performance.

Moreover, through the lithography process in NDL, we fabricated the RRAM device with small cell size. From the comparison of different cell sizes of RRAM, we examine the effect of characteristic caused by the cell size. Besides, we have shown great achievement on the endurance and retention test. The endurances for different cell size are all over 105 times and the retention are all more than 106 seconds. Moreover, we found the small size device demonstrated smaller resistance variation than the larger size ones.

Currently, RRAM device with crossbar array based on two-terminal resistance switches has been a possible solution. But there is an inherent problem for the architecture of crossbar, i.e., sneak current. To inhibit the sneak current, it requires a combination of a MOSFET selector or diode with the current RRAM device. As a future work, we need to combine our RRAM devices with MOSFETs as the structure of 1T1R. With the MOSFET, we can make sure that the resistance state of RRAM devices is always kept at high resistance state when we do not operate the RRAM device. Therefore, sneak current can be inhibited. Moreover, by the adjustment of the gate voltage to control the current on the set operation of the RRAM, we do not need to use the instrument to limit the operation current.