適用於FPGA的Hexagonal Search移動量偵測電路設計

Abstract

本論文主旨是在Xilinx Zynq 7020 FPGA平台上建構H.264/AVC移動量偵測電路的設計，透過AXI bus protocol，將H.264影片的raw data檔案從DDR SDRAM搬運到實作的電路上，以Hexagonal Search為策略進行block的移動量偵測。本論文分別以軟體以及硬體實作影像中移動量偵測的部份，並將所需計算的時間進行比較，預期能支援3張參考影像進行畫面間的移動偵測。主要的架構包含將block的searching area從DDR SDRAM中利用burst mode搬移到Block RAM之中，之後block進行interpolation時所需的sliding window的pixel來源的讀取就可從Block RAM中獲得，而無需再從DDR SDRAM中搬入，大大的降低傳輸的時間，最後設計出來的移動量偵測電路可以以100MHz在Zynq 7020 FPGA下運行。

In this thesis, we present the design of an H.264/AVC Hexagonal Search Motion Estimator IP for a Xilinx Zynq 7020 FPGA platform. The IP will read the chroma subsampling 4:2:0 yuv video data from the DDR SDRAM using the AXI bus protocol, and the hexagonal-based searching pattern is using for block motion estimation. The implementation in this thesis including both software and hardware, and it maintains three reference frames for inter prediction, and the running time of software and hardware will be compared. The IP is implemented by moving the searching area of the block from DDR SDRAM to Block RAM, and when interpolation is needed, the sliding window of the block can be acquired from the Block RAM instead of the DDR SDRAM, and the design reduces data transmission bandwidth significantly. The final design of the Hexagonal Search Motion Estimator IP can be verified using FPGA at 100MHz.