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dc.contributor.authorWei, Ting-Chenen_US
dc.contributor.authorLiu, Wei-Changen_US
dc.contributor.authorTseng, Chi-Yaoen_US
dc.contributor.authorLong, Syu-Siangen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.contributor.authorShiue, Muh-Tianen_US
dc.date.accessioned2014-12-08T15:02:37Z-
dc.date.available2014-12-08T15:02:37Z-
dc.date.issued2008en_US
dc.identifier.isbn978-1-4244-2018-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/1275-
dc.description.abstractAn OFDM baseband receiver chip for DVB-T/H application is proposed in this paper. With all-digital jointed detection/synchronization loops and channel estimation, the proposed receiver chip can compensate 200ppm sampling clock offset (SCO) and +/- 50 subcarrier spacing carrier frequency offset (CFO) in multipath environment The total memory requirement of this chip is 102.8KB and the total equivalent gate count (including memory) is about 806,800 gates. By using 0.18 mu m CMOS process, the power consumption is 28mW at 1.45 V, 40MHz and core size of this chip is 3600 mu m x 3600 mu m.en_US
dc.language.isoen_USen_US
dc.titleA 28mW OFDM Baseband Receiver Chip for DVB-T/H with All Digital Synchronizationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCEen_US
dc.citation.spage351en_US
dc.citation.epage354en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000262643900077-
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