使用有效的電路刺激產生法與邏輯修正以加速產品上市時間之研究

Abstract

產品從研發到上市的時間對於積體電路設計產業來說是最為關心的項目之一。提早將產品上市對於營收有著正面的影響，甚至可以造成初期壟斷的效果。但是由於快速成長的設計複雜度，設計上的錯誤更有可能避開矽前 (pre-silicon) 的驗證過程。花費在矽後 (post-silicon) 除錯與修正的時間可能會大幅延後產品上市的進度。

為了要鎖定一個矽後設計上的錯誤的位置，一個傳統的產業流程首先會分析可能的錯誤來源，接著縮減硬體模擬 (emulation) 或者FPGA原型的測試組，以確認錯誤是否還可被觀察到。受限於內部訊號的可見度，要找出錯誤的來源非常具有挑戰性。當上述方法失敗後，工程師可能會回歸到矽前的測試平台上建立新的測試情境 (scenario)，並且產生測試刺激 (stimuli) 來激發這些情境以偵測錯誤，而如何有效的產生刺激是這一步驟的主要議題。此一步驟一直持續到找出錯誤的位置為止。接著，工程師會以金屬層繞線及預先放置好的備用單元 (spare cell) 來修正錯誤，但是受限的實體資源可能無法適當的復原設計。在這情況下，必須持續提出額外的修正解法，直到該解法為實際可行為止。在這篇論文中，我們提出了加速產業流程中重複試行錯誤的有效解決方法。

為了精確的產生想要的測試刺激，我們提出了一個有效的覆蓋率導向(coverage-direct) 的刺激產生方法。與受限的隨機測試 (constrained random test) 和直接測試法不同，我們的方法可以自動為目標的測試情境產生刺激。不僅如此，我們同時考慮到多個情境 (多個情境可被單一刺激激發)，並提出了針對SystemVerilog語言中的功能覆蓋模型的應用。我們更進一步提出了合成 (synthesis) 此模型的技術，使其可當作硬體的檢查器或監視器來使用，因此可被整合進既有的方法中來增進內部訊號的可見度。

此外，我們設計了一個考慮到可用資源的邏輯函數修正方法，以解決邏輯修改的可行性問題。有別於將改正的過程分為兩個獨立步驟 (找出最小的邏輯差異及使用最少的資源來實行修改) 的既有方法，我們在產生修正函數的時候即考慮到實體的資訊，所以得出的修正函數有較高的可行性。使用業界測試用例的實驗結果顯示，修正函數的繞線成本可被我們的方法進一步改善。

Time to market is one of the most important concerns of the IC design industry. An early product release can have positive influence on the revenues and even creates a preliminary monopoly effect. However, due to the fast-growing design complexity, it is more likely that bugs escape the pre-silicon verification process. The efforts spent on post-silicon debugging and rectification may heavily postpone the schedule of product release.

To locate a bug in a post-silicon design, a conventional industrial flow first tries to analyze possible bug locations, and then narrows down the test suite for emulation or FPGA prototyping to see whether the bug is still observable. Because of the limited observability of internal signals, it is challenging to discover the root cause of the error. After failing to find the bug location, an engineer may return to the pre-silicon testbench, creates new test scenarios, and generates test stimuli to activate the scenarios for bug detection. How to generate stimuli efficiently is the major issue in this step. The process continues until the error location is uncovered. Then, an engineer proceeds to rectify the error using metal-layer wiring and pre-placed spare cells. However, the limited physical resources may fail to recover the design properly. In that case, other fixing solutions should be figured out, until a feasible rectification is derived. In this dissertation, we propose effective solutions to accelerate the trial-and-error iterations in the industrial flow.

For generating desired stimuli precisely, we propose an efficient coverage-driven stimulus generation method. Different from constrained-random test and directed test, our method automatically generates stimuli for target scenarios. Nevertheless, we consider the scenarios simultaneously (i.e., multiple scenarios can be activated by a single stimulus), and provide an application with the SystemVerilog functional coverage model. Furthermore, we also propose techniques to synthesize the coverage model, which can serve as a hardware checker or monitor. Then, it can be integrated into existing methods for observability improvement.

Besides, we devise a resource-aware functional logic rectification method to resolve the feasibility issue of logic correction. Unlike the existing methods that treat the rectification process as two independent steps (i.e., derive minimal logic difference and then implement it using minimal resources), we take the physical information into consideration during the generation of rectification functions. As a result, the derived rectification function has a better chance to be completed. The experimental results using industrial testcases demonstrate that the wire cost of the rectification function can be further improved by our approach.