標題: Feature detection for image analytics via FPGA acceleration
作者: Chang, H. -Y.
Jiang, I. H. -R.
Hofstee, H. P.
Jamsek, D.
Nam, G. -J.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-三月-2015
摘要: With the growth of multimedia data generation and consumption, image-based data analytics plays an increasingly important role in big data analytics systems. For image analytics, feature detection algorithms provide a foundation for a variety of image-based applications. These algorithms are typically computationally intensive and thus are good candidates for acceleration with field programmable gate arrays (FPGAs). In this paper, we investigate a Harris-Laplace variant of scale-invariant feature detection, a widely used image analytics algorithm, to demonstrate the capability of acceleration. Based on stream computing, we construct a fully pipelined implementation that can process one pixel per FPGA clock cycle. Our implementation significantly outperforms the existing published work. The proposed implementation adopts a single-precision floating-point representation and can detect the features of 640 x 480-pixel images at 540 frames per second. This throughput is sufficient for multistream real-time video interpretation.
URI: http://dx.doi.org/10.1147/JRD.2015.2398631
http://hdl.handle.net/11536/127938
ISSN: 0018-8646
DOI: 10.1147/JRD.2015.2398631
期刊: IBM JOURNAL OF RESEARCH AND DEVELOPMENT
Volume: 59
Issue: 2-3
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