標題: | Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation |
作者: | Hsiao, Yi-Hsuan Lue, Hang-Ting Chen, Wei-Chen Tsui, Bing-Yue Hsieh, Kuang-Yeu Lu, Chih-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Assisted gate;loading effect;three-dimensional (3D) NAND flash;VSAT;assisted gate;WL cut |
公開日期: | 1-十月-2015 |
摘要: | Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry. |
URI: | http://dx.doi.org/10.1109/LED.2015.2468723 http://hdl.handle.net/11536/128234 |
ISSN: | 0741-3106 |
DOI: | 10.1109/LED.2015.2468723 |
期刊: | IEEE ELECTRON DEVICE LETTERS |
Volume: | 36 |
Issue: | 10 |
起始頁: | 1015 |
結束頁: | 1017 |
顯示於類別: | 期刊論文 |