Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization

Abstract

Thermal-constrained task scheduler for throughput optimization on 3-D multicore processors (3-D MCPs) has been studied extensively. However, these throughput-optimized strategies often ignore energy consumption and overuse thermal simulations. Therefore, in this brief, a new strategy named thermal-aware mapping and VoltagE scaling (TAMVES) is proposed to optimize throughput and energy consumption while satisfying thermal constraints (in terms of both peak temperature and temperature gradient) simultaneously. Layer-by-layer task-to-core mapping and thermal-and-energy-aware voltage scaling are incorporated in TAMVES to reduce peak temperature and temperature gradient without extensive thermal simulation. Furthermore, idle time slots are also utilized by voltage scaling for minimizing energy consumption. Our experimental results show that under thermal constraints, TAMVES outperforms a previous work (3-D Wave) by 35.30% averagely on throughput. In addition, TAMVES that features three-order faster speed under timing constraints outperforms 3-D Wave for saving 51.17% more energy and reducing 8.37% more peak temperature and 5.67% more temperature gradient. As a result, TAMVES has proven itself an effective task scheduler that optimizes throughput and energy on 3-D MCPs under thermal constraints.