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dc.contributor.authorChen, Yi-Hangen_US
dc.contributor.authorChen, Yi-Tingen_US
dc.contributor.authorHuang, Juinn-Daren_US
dc.date.accessioned2015-12-02T03:00:49Z-
dc.date.available2015-12-02T03:00:49Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-2776-0en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/128469-
dc.description.abstractAs compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.en_US
dc.language.isoen_USen_US
dc.titleTwo-Staged Parallel Layer-Aware Partitioning for 3D Designsen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000356616400003en_US
dc.citation.woscount0en_US
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