标题: 9.9-mA 5-6 GHz CMOS Sub-Harmonic Direct-Conversion Receiver Using Deep N-Well BJT
作者: Chang, Wei-Ling
Meng, Chin-Chun
Syu, Jin-Siang
Wang, Chia-Ling
Huang, Guo-Wei
电机工程学系
Department of Electrical and Computer Engineering
关键字: Low power;low flicker noise;direct-conversion receiver;8-phase signal generator;sub-harmonic mixer;deep n-well vertical-NPN bipolar junction transistor
公开日期: 1-一月-2014
摘要: A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 mu m CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.
URI: http://hdl.handle.net/11536/128477
ISBN: 978-1-4799-1523-1
ISSN: 
期刊: 2014 IEEE 14TH TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS (SIRF)
起始页: 47
结束页: 49
显示于类别:Conferences Paper