完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chin, Albert | en_US |
dc.contributor.author | Yi, Shih-Han | en_US |
dc.date.accessioned | 2015-12-02T03:00:50Z | - |
dc.date.available | 2015-12-02T03:00:50Z | - |
dc.date.issued | 2014-01-01 | en_US |
dc.identifier.isbn | 978-1-4799-3627-4 | en_US |
dc.identifier.issn | en_US | |
dc.identifier.uri | http://hdl.handle.net/11536/128486 | - |
dc.description.abstract | Power consumption is the most crucial challenge for advanced IC with billions of transistors. High mobility Ge CMOS is one of the promising candidates to further lower the power consumption. Unfortunately, the ohmic contact in Ge nMOSFET suffers from Fermi-level pinning to valance band (E-V). It is also hard to form n(+)/p Ge junction by standard ion implantation due to the poor dopant activation by rapid thermal annealing (RTA) and fast impurity diffusion. Here high performance metal-gate/high-kappa/(111)-Ge nMOSFET was achieved with good 1.05 junction ideality factor (n), large similar to 5 orders on/off junction current, and higher mobility than SiO2/Si data at wide range carrier density (N-s) at small 0.85 nm equivalent-oxide thickness (EOT). The excellent n(+)/p Ge junction is attributed to the fast 30-ns laser annealing (LA) and YbGe2-x/n-Ge contact with less Fermi-level pinning. | en_US |
dc.language.iso | en_US | en_US |
dc.title | High Performance n(+)/p Junction Technology for High Mobility Ge nMOSFET | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2014 INTERNATIONAL WORKSHOP ON JUNCTION TECHNOLOGY (IWJT) | en_US |
dc.citation.spage | 140 | en_US |
dc.citation.epage | 143 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000355797900031 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |