完整後設資料紀錄
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dc.contributor.authorChin, Alberten_US
dc.contributor.authorYi, Shih-Hanen_US
dc.date.accessioned2015-12-02T03:00:50Z-
dc.date.available2015-12-02T03:00:50Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-3627-4en_US
dc.identifier.issnen_US
dc.identifier.urihttp://hdl.handle.net/11536/128486-
dc.description.abstractPower consumption is the most crucial challenge for advanced IC with billions of transistors. High mobility Ge CMOS is one of the promising candidates to further lower the power consumption. Unfortunately, the ohmic contact in Ge nMOSFET suffers from Fermi-level pinning to valance band (E-V). It is also hard to form n(+)/p Ge junction by standard ion implantation due to the poor dopant activation by rapid thermal annealing (RTA) and fast impurity diffusion. Here high performance metal-gate/high-kappa/(111)-Ge nMOSFET was achieved with good 1.05 junction ideality factor (n), large similar to 5 orders on/off junction current, and higher mobility than SiO2/Si data at wide range carrier density (N-s) at small 0.85 nm equivalent-oxide thickness (EOT). The excellent n(+)/p Ge junction is attributed to the fast 30-ns laser annealing (LA) and YbGe2-x/n-Ge contact with less Fermi-level pinning.en_US
dc.language.isoen_USen_US
dc.titleHigh Performance n(+)/p Junction Technology for High Mobility Ge nMOSFETen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 INTERNATIONAL WORKSHOP ON JUNCTION TECHNOLOGY (IWJT)en_US
dc.citation.spage140en_US
dc.citation.epage143en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000355797900031en_US
dc.citation.woscount0en_US
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