Stability/Performance Assessment of Monolithic 3D 6T/ST SRAM Cells Considering Transistor-Level Interlayer Coupling

Abstract

In this work, we investigate the impact of interlayer coupling on monolithic 3D 6T/8T SRAM cells with various layouts and tier combinations. Our results indicate that for 3D 6T SRAM cell with NFET in top layer, aligning upper-tier pull-down NFET with bottom-tier pull-up PFET enables better cell stability. For monolithic 3D 8T cell, an area-efficient 4N4P design is evaluated with optimized two-tier layout to enhance cell performance. We find that stacking NFET layer over the PFET tier results in larger design margins for SRAM cell stability and performance.