混合穿隧式場效電晶體與金氧半場效電晶體於單晶三維積體靜態隨機存取記憶體考慮層間電耦合的隨機變異特性之研究及分析

Abstract

本論文使用三維TCAD (Technology Computer Aided Design)蒙地卡羅 (Monte Carlo) 混合模式模擬器進行模擬，研究單晶三維層間電耦合對混合穿隧式場效電晶體與金氧半場效電晶體於靜態隨機存取記憶體的影響。本論文比較二維和三維的結果，並將混合式和傳統的靜態隨機存取記憶體作比較。此外，探討隨機變異特性對於單晶三維積體靜態隨機存取記憶體考慮層間電耦合後的影響。 TCAD模擬結果顯示在極低的操作電壓下(0.3伏特以下)二維的混合式靜態隨機存取記憶體相較於傳統的靜態隨機存取記憶體下擁有相同的漏電流、較優異的穩定性及單元性能。層間電耦合是利用下層電晶體的閘極電壓來改變上層電晶體的基板電壓，透過層間電耦合、不同的電晶體疊放和佈局規劃來改善單晶三維積體靜態隨機存取記憶體的穩定性及性能。其中一種最佳化的佈局和二維記憶體相比後呈現最佳的寫入穩定性及性能增益。然而，混合式比傳統式能夠提供更好的增益。此外，三維的記憶體能夠減少40%的單元面積。 本論文分析及比較功函數變異和線邊緣粗糙程度對於靜態隨機存取記憶體的穩定性、漏電及性能的影響。結果顯示功函數變異和線邊緣粗糙程度對於讀取擾度 (read disturb)和Vwrite,0有不同的影響。Vwrite,0由穿隧式場效電晶體及金氧半場效電晶體的驅動能力差異決定並大大地影響寫入穩定度。而記憶體的性能受到功函數變異和線邊緣粗糙程度對於閘極電容的變異性影響。

This thesis investigates the impact of interlayer coupling on the stability and performance of monolithic 3D 7T SRAM cell composed of TFETs and MOSFETs operating at ultra-low voltage. We compare the 3D result with 2D counterparts, and compared hybrid case with pure MOSFET case. In addition, we investigate the impact of WFV and LER for monolithic 3D SRAMs considering interlayer coupling. TCAD simulation result indicates that the planar (2D) 7T hybrid TFET-MOSFET SRAM cell exhibits equal leakage, better stability and performance compared with the conventional 2D 8T MOSFET SRAM at ultra-low voltage (VDD ≤ 0.3V). The interlayer coupling, where the front-gate of the bottom tier device alters the back gate bias of the upper tier device, and various stacking and layout arrangements are examined and exploited to improve the stability and performance of monolithic 3D SRAMs. An optimized 3D design is shown to exhibit the best WSNM and cell write performance improvement over the planar design. However, the hybrid case has better improvement than pure MOSFET case. Furthermore, 3D SRAM designs reduce cell area by 40%. The impacts of work function variation (WFV) and line edge roughness (LER) on SRAM cell stability, leakage power and performance are investigated and compared. The results indicate that WFV and LER have different impacts on read disturb and Vwrite,0, which dominate SRAM stability and is determined by the distinct current drive of TFET and MOSFET. The performance is influenced by the different variations of gate capacitance (Cg) under WFV and LER.