完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLin, Yi-Minen_US
dc.contributor.authorWu, Jau-Yeten_US
dc.contributor.authorLin, Chien-Chingen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.date.accessioned2014-12-08T15:17:51Z-
dc.date.available2014-12-08T15:17:51Z-
dc.date.issued2009en_US
dc.identifier.isbn978-981-08-2468-6en_US
dc.identifier.urihttp://hdl.handle.net/11536/12934-
dc.description.abstractIn this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13 mu m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.en_US
dc.language.isoen_USen_US
dc.titleA Long Block Length BCH Decoder for DVB-S2 Applicationen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE 2009 12TH INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS (ISIC 2009)en_US
dc.citation.spage300en_US
dc.citation.epage303en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000290361900075-
顯示於類別:會議論文