高面積效益軟性BCH及RS解碼器

Abstract

本論文由演算法到架構設計與電路實現探討軟性BCH跟RS碼解碼器。依解碼方式不同可分成EM類型以及Chase類型解碼方式兩個主要部分做討論。 軟性錯誤更正碼解碼可以在維持相同碼率的前提下提升錯誤更正能力，而其中軟性BCH跟RS碼已經引起許多的研究風潮。和傳統的硬性解碼器相比，軟性解碼器雖能提供較好的更正能力，但必須付出高額的硬體代價。本論文首先提出EM類型解碼器來針對最不可靠的位置解碼以降低硬體複雜度。低複雜度EM類型解碼和傳統硬性解碼器相比，可以提供比較低的硬體複雜度，但是必須接受較高可靠度的資訊才能維持住錯誤更正能力。另一方面，高效能EM類型解碼使用和低複雜度EM類型解碼相似的概念，但是提供一個錯誤補償方式在非不可靠位置額外更正一個錯誤。因而，其軟性解碼器可以在提供和硬性解碼器相似的硬體複雜度前提下擁有較好的錯誤更正能力。 本論文提出了Chase類型解碼演算法來提供更通用的BCH跟RS碼軟性解碼方式。不像傳統Chase解碼器同時使用多個硬性解碼器來解多個候選數列產生其對應候選碼，所提出的簡易決定軟性解碼方式只需一個硬性解碼器即可執行Chase演算法。此外，透過漢明距離的運算，一個簡化的決定器被設計來決定最有可能的候選碼。而在所提出的限定決定解碼演算法中，可進一步地省略決定器的運算。透過限定由關鍵方程式運算器產生的錯誤位置方程式的次數，所提出的解碼方式只需完整解碼一組候選數列。 基於上述各項技術，我們實作了四個解碼器。一個26.9 K 314.5 Mb/s 的軟性BCH (32400, 32208; 12) 解碼器晶片使用低複雜度EM類型解碼方式首先被設計應用在DVB-S2系統上。實現在90奈米製程下，所提出的軟性BCH解碼器可以提供314.5 Mb/s 的資料輸出量，且和一個擁有99.3 Mb/s資料輸出量的傳統硬性BCH解碼器相比，其邏輯閘數量僅有硬性解碼器的一半。第二個解碼器則是將高效益EM類型解碼方式應用BCH (255, 239; 2) 跟BCH (255, 231; 3) 解碼器上。和傳統硬性解碼器相比，所設計的軟性BCH解碼器透過錯誤補償的方式最多可在10^-5 BER下得到0.75 dB的更正效能增益，同時擁有5%的硬體複雜度改善。第三個解碼器是應用在mmWave系統的軟性RS (224, 216; 4) 解碼器，其使用簡易決定軟性解碼方式用以達到30 K邏輯閘數和2.5 Gb/s的資料輸出量。和傳統的硬性解碼相比，可在10^-5 BER時擁有0.5 dB的更正效能增益。最後一個解碼器則是設計於光通訊系統的軟性RS (255, 239; 8) 解碼器。其使用限定決定軟性解碼方式用以達到45.3 K邏輯閘數和2.56 Gb/s的資料輸出量。且在10^-4 CER下可比硬性解碼器多擁有0.4 dB的更正效能。所有的實驗結果皆顯示我們所提的方式能得到如預期的成效。

This dissertation investigates the soft BCH and RS decoders from algorithms to architecture designs and circuit implementation. Two different decoding schemes are studied, including the error magnitude (EM) type and Chase-type soft decoding algorithms. For higher error correcting performance with the same code rate, soft decoding algorithms of error control codes are the most popular methods and have aroused many research interests in BCH and RS decoding. As compared with traditional hard decoders, soft decoders provide better error correcting performance but much higher hardware complexity. In this dissertation, the EM-type soft decoding algorithms are firstly proposed for BCH codes to provide low hardware complexity by dealing with the least reliable bits. The low complexity EM-type approach can provide lower hardware complexity than the hard decoder but has to exploit higher reliable soft information for maintaining the error correcting performance. On the other hand, the high performance EM-type approach has similar concept as low complexity EM-type approach but compensates one extra error outside the least reliable set, leading to better performance while providing comparable hardware complexity. The Chase-type soft decoding algorithms are discussed for providing more general low complexity decoding methods for both BCH and RS codes. Instead of utilizing various hard decoders to decode all candidate sequences simultaneously, a decision-eased soft decodingscheme is provided to process Chase algorithm with one hard decoder module. In addition, a simplified decision making unit is proposed to determine the most likely codeword with Hamming distance calculations. Moreover, the decision making unit can be eliminated with the proposed decision-confined soft decoding algorithm. By confining the degree of error location polynomial generated from the key equation solver, our proposal only needs to completely decode one candidate sequence. Four implemented works are presented in this dissertation. A 26.9 K 314.5 Mb/s soft (32400, 32208; 12) BCH decoder chip is designed for DVB-S2 system based on low complexity EM-type approach. The proposed soft BCH decoder can achieve 314.5 Mb/s with 50.0% gate-count reduction in contrast to a 99.3 Mb/s traditional hard BCH decoder in CMOS 90 nm technology. The second designs are high performance EM-type soft BCH (255, 239; 2) and (255, 231; 3) decoders. Our proposed soft BCH decoders can achieve at most 0.75 dB coding gain at 10^-5 BER with one extra error compensation and 5% less area than traditional hard BCH decoders. The third design is a 30 K 2.5 Gb/s decision-eased soft RS (224, 216; 4) decoder for millimeter-wave (mmWave) system, which has 0.5 dB coding gain at 10^-5 BER as compared with the conventional hard decoder. The remaining design is a decision-confined soft RS (255, 239; 8) decoder chip for optical communications, which can provide 0.4 dB coding gain at 10^-4 CER over hard decoders and achieve 2.56 Gb/s throughput with gate count of 45.3 K. All the implementation results reveal the positive consequence as expected.