標題: Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off
作者: Cheng, Ya-Chi
Chen, Hung-Bin
Chang, Chun-Yen
Wu, Yi-Kang
Shih, Yi-Jia
Shao, Chi-Shen
Wu, Yung-Chun
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2-Nov-2015
摘要: A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.
URI: http://dx.doi.org/10.1063/1.4935247
http://hdl.handle.net/11536/129388
ISSN: 0003-6951
DOI: 10.1063/1.4935247
期刊: APPLIED PHYSICS LETTERS
Volume: 107
Issue: 18
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