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dc.contributor.authorFang, Wai-Chien_US
dc.contributor.authorChang, Jui-Chungen_US
dc.contributor.authorHuang, Kuan-Juen_US
dc.contributor.authorFeng, Chih-Weien_US
dc.contributor.authorChou, Chia-Chingen_US
dc.date.accessioned2016-03-28T00:05:41Z-
dc.date.available2016-03-28T00:05:41Z-
dc.date.issued2014-01-01en_US
dc.identifier.isbn978-1-4799-2346-5en_US
dc.identifier.issn2163-4025en_US
dc.identifier.urihttp://hdl.handle.net/11536/129759-
dc.description.abstractThis paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the critical computational latency is associated with the SVD process. Accordingly, the performance of the SVD processor should be prioritized. Going beyond previous research [1], this work presents a novel design of coordinate rotation digital computer (CORDIC) engine which is optimized and speeded up to avoid structural hazards. Finally, the processor is fabricated using TSMC 40nm CMOS technology in a 16-channel EEG system. The computation time of the SVD processor is reduced by 24.7% and the average correlation coefficient between original source signals and extracted ORICA signals is 0.95452.en_US
dc.language.isoen_USen_US
dc.titleAn Efficient VLSI Implementation of SVD Processor of On-line Recursive ICA for Real-time EEG Systemen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS)en_US
dc.citation.spage73en_US
dc.citation.epage76en_US
dc.contributor.department電機工程學系zh_TW
dc.contributor.departmentDepartment of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000366049300019en_US
dc.citation.woscount0en_US
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